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Searched refs:x3 (Results 1 – 25 of 195) sorted by relevance

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/trusted-firmware-a/plat/hisilicon/hikey/
A Dhisi_pwrc_sram.S29 mrs x3, actlr_el3
30 orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
31 msr actlr_el3, x3
33 mrs x3, actlr_el2
34 orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT
35 msr actlr_el2, x3
37 ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD
42 pen: ldr x4, [x3, x0, LSL #3]
48 mov x3, #0x0
/trusted-firmware-a/lib/libc/aarch64/
A Dmemset.S22 mov x3, x0 /* keep x0 */
28 strb w1, [x3], #1
31 tst x3, #7
45 stp x1, x1, [x3], #16 /* write 64 bytes in a loop */
50 stp x1, x1, [x3], #16 /* write 32 bytes */
51 stp x1, x1, [x3], #16
53 stp x1, x1, [x3], #16 /* write 16 bytes */
55 str x1, [x3], #8 /* write 8 bytes */
57 str w1, [x3], #4 /* write 4 bytes */
59 strh w1, [x3], #2 /* write 2 bytes */
[all …]
/trusted-firmware-a/plat/nxp/soc-ls1028a/aarch64/
A Dls1028a.S151 mov x3, x30
163 mov x30, x3
176 mov x3, x30
197 mov x30, x3
367 orr x3, x3, #OSDLR_EL1_DLK_LOCK
422 cmp x2, x3
486 bic x3, x3, #OSDLR_EL1_DLK_LOCK
1022 lsl x3, x3, x0
1034 lsr x3, x3, #1
1079 lsl x3, x3, x0
[all …]
/trusted-firmware-a/plat/nxp/common/aarch64/
A Dbl31_data.S161 clz x3, x0
174 add x3, x3, x1
185 mul x3, x3, x0
200 sub x3, x3, x1
208 dc cvac, x3
224 clz x3, x0
237 add x3, x3, x2
248 mul x3, x3, x0
263 sub x3, x3, x2
434 mov x3, #2
[all …]
/trusted-firmware-a/plat/imx/common/
A Dimx_sip_svc.c22 u_register_t x3, in imx_sip_handler() argument
30 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
34 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
39 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
41 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
44 SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
49 SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
53 SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle)); in imx_sip_handler()
57 SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
A Dimx_sip_handler.c42 u_register_t x3, in imx_srtc_handler() argument
49 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
73 u_register_t x3) in imx_cpufreq_handler() argument
77 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
96 u_register_t x3) in imx_wakeup_src_handler() argument
141 u_register_t x3, in imx_misc_set_temp_handler() argument
153 u_register_t x3, in imx_src_handler() argument
181 u_register_t x3, in imx_get_commit_hash() argument
207 u_register_t x3, in imx_buildinfo_handler() argument
226 u_register_t x3, in imx_kernel_entry_handler() argument
[all …]
/trusted-firmware-a/plat/imx/common/include/
A Dimx_sip_svc.h38 u_register_t x2, u_register_t x3,
42 u_register_t x2, u_register_t x3);
47 u_register_t x2, u_register_t x3, void *handle);
52 u_register_t x2, u_register_t x3);
54 u_register_t x2, u_register_t x3, u_register_t x4);
56 u_register_t x2, u_register_t x3);
60 u_register_t x2, u_register_t x3,
64 u_register_t x2, u_register_t x3,
/trusted-firmware-a/plat/arm/board/tc/include/
A Dtc_helpers.S36 lsl x3, x0, #MPIDR_AFFINITY_BITS
37 csel x3, x3, x0, eq
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a/services/std_svc/
A Dstd_svc_setup.c82 u_register_t x3, in std_svc_smc_handler() argument
93 x3 &= UINT32_MAX; in std_svc_smc_handler()
116 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
134 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
145 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
152 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
159 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
169 return rmmd_gtsi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
176 return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
A Dpci_svc.c44 u_register_t x3, in pci_smc_handler() argument
73 if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { in pci_smc_handler()
79 if (pci_read_config(x1, x2, x3, &ret) != 0U) { in pci_smc_handler()
89 if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) { in pci_smc_handler()
92 ret = pci_write_config(x1, x2, x3, x4); in pci_smc_handler()
101 if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) { in pci_smc_handler()
/trusted-firmware-a/plat/arm/board/arm_fpga/aarch64/
A Dfpga_helpers.S80 ldr x3, [x1, x0, LSL #PLAT_FPGA_HOLD_ENTRY_SHIFT]
81 cmp x3, #PLAT_FPGA_HOLD_STATE_GO
86 ldr x3, [x2]
87 br x3
136 lsl x3, x0, #MPIDR_AFFINITY_BITS
137 csel x3, x3, x0, eq
140 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
141 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
142 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a/plat/arm/css/sgm/aarch64/
A Dcss_sgm_helpers.S38 lsr x3, x0, #MPIDR_AFFINITY_BITS
39 csel x3, x3, x0, eq
42 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a/plat/mediatek/common/
A Dmtk_sip_svc.c28 u_register_t x3, in mediatek_plat_sip_handler() argument
43 u_register_t x3, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
94 u_register_t x3, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/trusted-firmware-a/lib/pmf/
A Dpmf_smc.c20 u_register_t x3, in pmf_smc_handler() argument
33 x3 = (uint32_t)x3; in pmf_smc_handler()
43 (unsigned int)x3, &ts_value); in pmf_smc_handler()
56 (unsigned int)x3, &ts_value); in pmf_smc_handler()
/trusted-firmware-a/lib/aarch64/
A Dmisc_helpers.S392 orr x3, x0, x1
393 tst x3, #0xf
529 1: ldr x3, [x1]
532 cmp x3, x6
536 cmp x3, x7
538 add x3, x3, x0
539 str x3, [x1]
569 1: ldr x3, [x1, #8]
570 cbz x3, 2f
578 add x3, x0, x3
[all …]
A Dcache_helpers.S25 dcache_line_size x2, x3
27 sub x3, x2, #1
28 bic x0, x0, x3
84 ubfx x3, x9, \shift, \fw
85 lsl x3, x3, \ls
91 cbz x3, exit
142 cmp x3, x10
173 mov x3, \level
174 sub x10, x3, #2
/trusted-firmware-a/bl31/aarch64/
A Dea_delegate.S67 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
113 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
179 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
180 cmp x3, #SYNC_EA_FSC
215 ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH
216 cmp x3, #DFSC_SERROR
246 mrs x3, elr_el3
247 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
267 mov x3, sp
302 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
[all …]
/trusted-firmware-a/plat/nxp/soc-lx2160a/aarch64/
A Dlx2160a.S205 mov x3, x30
228 mov x30, x3
399 mrs x3, osdlr_el1
400 orr x3, x3, #OSDLR_EL1_DLK_LOCK
401 msr osdlr_el1, x3
453 cmp x2, x3
513 mrs x3, osdlr_el1
514 bic x3, x3, #OSDLR_EL1_DLK_LOCK
667 str w1, [x3, x0]
936 str w4, [x2, x3]
[all …]
A Dlx2160a_warm_rst.S40 mov x3, xzr
43 mov x3, #1
60 cbz x3, touch_line1
82 cbz x3, touch_line2
103 cbz x3, touch_line3
124 cbz x3, touch_line4
149 cbz x3, touch_line6
170 cbz x3, touch_line5
198 cbz x3, touch_line6
227 cbz x3, start_line0
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/
A Dplat_trampoline.S49 ldp x3, x4, [x1], #16
50 stp x3, x4, [x0], #16
135 mov x3, #MC_SECURITY_CFG3_0
136 ldr w1, [x0, x3]
138 mov x3, #MC_SECURITY_CFG0_0
139 ldr w2, [x0, x3]
140 orr x3, x1, x2 /* TZDRAM base */
147 str x0, [x3, x2] /* set value in TZDRAM */
/trusted-firmware-a/plat/arm/board/fvp/aarch64/
A Dfvp_helpers.S163 lsl x3, x0, #MPIDR_AFFINITY_BITS
164 csel x3, x3, x0, eq
167 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
168 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
169 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/trusted-firmware-a/plat/arm/common/
A Darm_sip_svc.c46 u_register_t x3, in arm_sip_handler() argument
61 return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
70 return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
79 return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
97 (uint32_t) x1, (uint32_t) x2, (uint32_t) x3, in arm_sip_handler()
/trusted-firmware-a/plat/mediatek/mt8192/
A Dplat_sip_calls.c18 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); in mediatek_plat_sip_handler()
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/trusted-firmware-a/plat/nxp/common/sip_svc/
A Dsip_svc.c29 u_register_t x3, in nxp_plat_sip_handler() argument
64 u_register_t x3, in nxp_sip_handler() argument
75 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in nxp_sip_handler()
140 ret = el2_2_aarch32(smc_fid, x1, x2, x3); in nxp_sip_handler()
151 return nxp_plat_sip_handler(smc_fid, x1, x2, x3, x4, in nxp_sip_handler()
160 u_register_t x3, in sip_smc_handler() argument
181 return nxp_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/trusted-firmware-a/plat/marvell/armada/common/
A Dmrvl_sip_svc.c76 u_register_t x3, in mrvl_sip_smc_handler() argument
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); in mrvl_sip_smc_handler()
127 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4); in mrvl_sip_smc_handler()
150 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
154 ret = mvebu_dfx_misc_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()

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