| /trusted-firmware-a/plat/nxp/common/psci/aarch64/ |
| A D | psci_utils.S | 244 bic x4, x4, #CPUECTLR_SMPEN_MASK
257 orr x4, x4, #SCR_FIQ_MASK
426 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
469 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
560 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
692 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
777 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
788 bic x4, x4, #CPUECTLR_SMPEN_MASK
894 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
982 orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
[all …]
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| /trusted-firmware-a/plat/arm/board/morello/aarch64/ |
| A D | morello_helper.S | 34 mov x4, x0
42 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
48 mov x4, #MORELLO_MAX_CLUSTERS_PER_CHIP
49 madd x2, x3, x4, x2
50 mov x4, #MORELLO_MAX_CPUS_PER_CLUSTER
51 madd x1, x2, x4, x1
52 mov x4, #MORELLO_MAX_PE_PER_CPU
[all …]
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| /trusted-firmware-a/plat/arm/board/n1sdp/aarch64/ |
| A D | n1sdp_helper.S | 33 mov x4, x0
41 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
47 mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
48 madd x2, x3, x4, x2
49 mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
50 madd x1, x2, x4, x1
51 mov x4, #N1SDP_MAX_PE_PER_CPU
[all …]
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| /trusted-firmware-a/plat/arm/css/sgi/aarch64/ |
| A D | sgi_helper.S | 38 mov x4, x0
46 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
47 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
48 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
49 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
52 mov x4, #PLAT_ARM_CLUSTER_COUNT
53 madd x2, x3, x4, x2
54 mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
55 madd x1, x2, x4, x1
56 mov x4, #CSS_SGI_MAX_PE_PER_CPU
[all …]
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| /trusted-firmware-a/plat/arm/board/arm_fpga/ |
| A D | kernel_trampoline.S | 32 adr x4, _tramp_start
33 orr x4, x4, #0x1fffff
34 add x4, x4, #1 /* align up to 2MB */
35 br x4
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| /trusted-firmware-a/lib/xlat_mpu/aarch64/ |
| A D | enable_mpu.S | 40 mrs x4, sctlr_el2
42 orr x4, x4, x5
45 bic x5, x4, #SCTLR_C_BIT
47 csel x4, x5, x4, ne
49 msr sctlr_el2, x4
|
| /trusted-firmware-a/common/aarch64/ |
| A D | debug.S | 41 udiv x0, x4, x5 /* Get the quotient */
42 msub x4, x0, x5, x4 /* Find the remainder */
75 adr x4, assert_msg1
77 mov x4, x5
79 adr x4, assert_msg2
85 mov x4, x6
102 ldrb w0, [x4], #0x1
123 lsrv x0, x4, x5
203 adr x4, panic_msg
205 mov x4, x6
[all …]
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| /trusted-firmware-a/plat/hisilicon/hikey/aarch64/ |
| A D | hikey_helpers.S | 105 adr x4, plat_err_str
108 adr x4, esr_el3_str
111 mrs x4, esr_el3
114 adr x4, elr_el3_str
117 mrs x4, elr_el3
122 adr x4, plat_err_str
125 adr x4, esr_el1_str
128 mrs x4, esr_el1
131 adr x4, elr_el1_str
134 mrs x4, elr_el1
|
| /trusted-firmware-a/include/plat/arm/common/aarch64/ |
| A D | arm_macros.S | 76 adr x4, gicd_pend_reg
79 sub x4, x7, x16
80 cmp x4, #0x280
84 adr x4, prefix
88 sub x4, x7, x16
92 adr x4, spacer
95 ldr x4, [x7], #8
98 adr x4, newline
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| /trusted-firmware-a/plat/hisilicon/hikey960/aarch64/ |
| A D | hikey960_helpers.S | 109 adr x4, plat_err_str
112 adr x4, esr_el3_str
115 mrs x4, esr_el3
118 adr x4, elr_el3_str
121 mrs x4, elr_el3
126 adr x4, plat_err_str
129 adr x4, esr_el1_str
132 mrs x4, esr_el1
135 adr x4, elr_el1_str
138 mrs x4, elr_el1
|
| /trusted-firmware-a/services/std_svc/ |
| A D | std_svc_setup.c | 83 u_register_t x4, in std_svc_smc_handler() argument
94 x4 &= UINT32_MAX; in std_svc_smc_handler()
116 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
134 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
145 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
152 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
159 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
169 return rmmd_gtsi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
176 return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
|
| /trusted-firmware-a/plat/amlogic/common/include/ |
| A D | plat_macros.S | 49 adr x4, gicd_pend_reg
53 sub x4, x7, x16
54 cmp x4, #0x280
58 adr x4, spacer
61 ldr x4, [x7], #8
64 adr x4, newline
|
| /trusted-firmware-a/bl31/aarch64/ |
| A D | crash_reporting.S | 91 mov x4, x6
95 sub x0, x4, x6
97 mov x6, x4
118 add x4, x4, x0
228 mov x4, x6
232 sub x0, x4, x6
234 mov x6, x4
250 ldr x4, [x7]
278 bic x4, x4, x2
346 mov x4, sp
[all …]
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| /trusted-firmware-a/plat/mediatek/common/ |
| A D | mtk_sip_svc.c | 29 u_register_t x4, in mediatek_plat_sip_handler() argument
44 u_register_t x4, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
95 u_register_t x4, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
|
| /trusted-firmware-a/lib/xlat_tables_v2/aarch64/ |
| A D | enable_mmu.S | 72 _mrs x4, sctlr, \el
74 orr x4, x4, x5
77 bic x5, x4, #SCTLR_C_BIT
79 csel x4, x5, x4, ne
81 _msr sctlr, \el, x4
|
| /trusted-firmware-a/plat/hisilicon/hikey/include/ |
| A D | plat_macros.S | 50 adr x4, gicd_pend_reg
53 sub x4, x7, x16
54 cmp x4, #0x280
57 adr x4, spacer
59 ldr x4, [x7], #8
61 adr x4, newline
|
| /trusted-firmware-a/plat/hisilicon/hikey960/include/ |
| A D | plat_macros.S | 50 adr x4, gicd_pend_reg
53 sub x4, x7, x16
54 cmp x4, #0x280
57 adr x4, spacer
59 ldr x4, [x7], #8
61 adr x4, newline
|
| /trusted-firmware-a/plat/renesas/common/include/ |
| A D | plat_macros.S | 45 adr x4, gicd_pend_reg
48 sub x4, x7, x16
49 cmp x4, #0x280
52 adr x4, spacer
54 ldr x4, [x7], #8
56 adr x4, newline
|
| /trusted-firmware-a/plat/mediatek/mt6795/include/ |
| A D | plat_macros.S | 42 adr x4, gicd_pend_reg
45 sub x4, x7, x16
46 cmp x4, #0x280
50 adr x4, spacer
53 ldr x4, [x7], #8
56 adr x4, newline
|
| /trusted-firmware-a/plat/mediatek/mt8173/include/ |
| A D | plat_macros.S | 48 adr x4, gicd_pend_reg
51 sub x4, x7, x16
52 cmp x4, #0x280
56 adr x4, spacer
59 ldr x4, [x7], #8
62 adr x4, newline
|
| /trusted-firmware-a/plat/mediatek/mt8183/include/ |
| A D | plat_macros.S | 48 adr x4, gicd_pend_reg
51 sub x4, x7, x26
52 cmp x4, #0x280
56 adr x4, spacer
59 ldr x4, [x7], #8
62 adr x4, newline
|
| /trusted-firmware-a/plat/mediatek/mt8192/ |
| A D | plat_sip_calls.c | 19 u_register_t x4, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
31 SMC_RET2(handle, ret, x4); in mediatek_plat_sip_handler()
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); in mediatek_plat_sip_handler()
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
|
| /trusted-firmware-a/plat/nvidia/tegra/include/ |
| A D | plat_macros.S | 46 adr x4, gicd_pend_reg
49 sub x4, x7, x16
50 cmp x4, #0x280
53 adr x4, spacer
57 adr x4, newline
|
| /trusted-firmware-a/plat/qti/common/inc/aarch64/ |
| A D | plat_macros.S | 85 adr x4, gicd_pend_reg
88 sub x4, x7, x26
89 cmp x4, #0x280
93 adr x4, spacer
96 ldr x4, [x7], #8
99 adr x4, newline
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| /trusted-firmware-a/plat/xilinx/versal/include/ |
| A D | plat_macros.S | 76 adr x4, gicd_pend_reg
79 sub x4, x7, x16
80 cmp x4, #0x280
84 adr x4, spacer
87 ldr x4, [x7], #8
90 adr x4, newline
|