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/trusted-firmware-a/plat/nxp/common/aarch64/
A Dbl31_data.S392 dc cvac, x5
394 dc cvac, x5
396 dc cvac, x5
398 dc cvac, x5
400 dc cvac, x5
402 dc cvac, x5
404 dc cvac, x5
406 dc cvac, x5
408 dc cvac, x5
435 sub x5, x5, #SEC_REGION_SIZE
[all …]
/trusted-firmware-a/plat/rockchip/rk3399/drivers/pmu/
A Dplat_pmu_macros.S43 lsr x5, x0, #6
44 ldr w3, [x4, x5]
45 str wzr, [x4, x5]
89 mov x5, PMU_BASE
90 ldr w0, [x5, #PMU_SFT_CON]
93 str w0, [x5, #PMU_SFT_CON]
96 ldr w1, [x5, #PMU_DDR_SREF_ST]
110 mov x5, CRU_BASE
116 mov x5, PMU_BASE
117 ldr w0, [x5, #PMU_SFT_CON]
[all …]
/trusted-firmware-a/plat/nxp/common/psci/aarch64/
A Dpsci_utils.S415 mov x0, x5
432 mov x0, x5
436 mov x0, x5
457 mov x5, x0
462 mov x0, x5
475 mov x0, x5
493 mov x5, x0
498 mov x0, x5
507 mov x0, x5
629 mov x0, x5
[all …]
/trusted-firmware-a/plat/marvell/armada/a8k/common/aarch64/
A Dplat_helpers.S92 mrs x5, s3_1_c11_c0_2 /* L2 Ctrl */
93 orr x5, x5, #(1 << 21) /* Enable L1/L2 cache ECC & Parity */
94 msr s3_1_c11_c0_2, x5 /* L2 Ctrl */
103 mrs x5, s3_1_c15_c0_0 /* L2 Ctrl */
104 orr x5, x5, #(1 << 14) /* Enable UniqueClean evictions with data */
105 msr s3_1_c15_c0_0, x5 /* L2 Ctrl */
/trusted-firmware-a/common/aarch64/
A Ddebug.S39 mov x5, #MAX_DEC_DIVISOR
41 udiv x0, x4, x5 /* Get the quotient */
42 msub x4, x0, x5, x4 /* Find the remainder */
45 udiv x5, x5, x6 /* Reduce divisor */
46 cbnz x5, dec_print_loop
65 mov x5, x0
77 mov x4, x5
116 mov x5, #64 /* No of bits to convert to ascii */
122 sub x5, x5, #4
123 lsrv x0, x4, x5
[all …]
/trusted-firmware-a/plat/rockchip/common/pmusram/
A Dcpus_on_fixed_addr.S23 adr x5, sys_sleep_flag_sram
24 ldr w2, [x5, #PSRAM_DT_PM_FLAG]
30 adr x5, sys_sleep_flag_sram
31 ldr x1, [x5, #PSRAM_DT_SP]
34 ldr x1, [x5, #PSRAM_DT_DDR_FUNC]
/trusted-firmware-a/plat/qti/common/src/
A Dqti_syscall.c181 x5 = (uint32_t) x5; in qti_sip_mem_assign()
184 if ((x1 != QTI_SIP_SVC_MEM_ASSIGN_PARAM_ID) || (x5 == 0x0)) { in qti_sip_mem_assign()
190 dyn_map_start = x5; in qti_sip_mem_assign()
202 x6 = *((uint32_t *) x5 + 1); in qti_sip_mem_assign()
203 x7 = *((uint32_t *) x5 + 2); in qti_sip_mem_assign()
204 x5 = *(uint32_t *) x5; in qti_sip_mem_assign()
206 x6 = *((uint64_t *) x5 + 1); in qti_sip_mem_assign()
207 x7 = *((uint64_t *) x5 + 2); in qti_sip_mem_assign()
208 x5 = *(uint64_t *) x5; in qti_sip_mem_assign()
225 dyn_map_end = MAX((x2 + x3), (x4 + x5)); in qti_sip_mem_assign()
[all …]
/trusted-firmware-a/lib/xlat_mpu/aarch64/
A Denable_mpu.S41 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
42 orr x4, x4, x5
45 bic x5, x4, #SCTLR_C_BIT
47 csel x4, x5, x4, ne
/trusted-firmware-a/bl31/aarch64/
A Dea_delegate.S68 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
114 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
239 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
240 cbz x5, 1f
254 mrs x5, esr_el3
255 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
271 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
273 mov sp, x5
A Dcrash_reporting.S83 mrs x5, tpidr_el3
84 add x5, x5, #CPU_DATA_CRASH_BUF_SIZE
86 cmp x7, x5
339 stp x4, x5, [x0, #REGSZ * 4]
/trusted-firmware-a/plat/nxp/common/ocram/aarch64/
A Docram.S28 stp x4, x5, [sp, #-16]!
41 ldp x4, x5, [x0]
45 stp x4, x5, [x0]
69 ldp x4, x5, [sp], #16
/trusted-firmware-a/lib/xlat_tables_v2/aarch64/
A Denable_mmu.S73 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
74 orr x4, x4, x5
77 bic x5, x4, #SCTLR_C_BIT
79 csel x4, x5, x4, ne
/trusted-firmware-a/plat/nxp/soc-ls1028a/aarch64/
A Dls1028a.S67 stp x4, x5, [sp, #-16]!
91 ldp x4, x5, [sp], #16
233 mov x5, #NXP_GICD_ADDR
314 mov x5, x0
411 mov x5, x30
440 mov x30, x5
453 mov x5, x0
459 mov x0, x5
471 mov x0, x5
1048 ldr x5, =NXP_EPU_ADDR
[all …]
/trusted-firmware-a/plat/rockchip/rk3399/
A Dplat_sip_calls.c60 uint64_t x5, x6; in rockchip_plat_sip_handler() local
70 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in rockchip_plat_sip_handler()
72 SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6)); in rockchip_plat_sip_handler()
/trusted-firmware-a/plat/nxp/soc-lx2160a/aarch64/
A Dlx2160a.S84 stp x4, x5, [sp, #-16]!
112 ldp x4, x5, [sp], #16
266 mov x5, #NXP_GICD_ADDR
348 mov x5, x0
443 mov x5, x30
470 mov x30, x5
483 mov x5, x0
489 mov x0, x5
502 mov x0, x5
1015 ldr x5, =DEVDISR2_MASK
[all …]
A Dlx2160a_warm_rst.S117 mov x5, xzr
119 add x5, x5, #1
120 cmp x5, #COUNT_100
/trusted-firmware-a/plat/arm/board/tc/include/
A Dtc_helpers.S47 mov x5, #PLAT_MAX_PE_PER_CPU
48 madd x0, x1, x5, x0
/trusted-firmware-a/plat/rockchip/rk3399/drivers/dp/
A Dcdn_dp.c54 uint64_t x5, in dp_hdcp_store_key() argument
65 hdcp_key_pdata[4] = x5; in dp_hdcp_store_key()
/trusted-firmware-a/plat/arm/css/sgm/aarch64/
A Dcss_sgm_helpers.S49 mov x5, #PLAT_MAX_PE_PER_CPU
50 madd x0, x1, x5, x0
/trusted-firmware-a/plat/arm/board/arm_fpga/aarch64/
A Dfpga_helpers.S69 mov x5, #VALID_MPID
145 mov x5, #FPGA_MAX_PE_PER_CPU
149 madd x0, x1, x5, x0
/trusted-firmware-a/plat/marvell/armada/common/
A Dmrvl_sip_svc.c82 u_register_t ret, read, x5 = x1; in mrvl_sip_smc_handler() local
96 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
/trusted-firmware-a/include/lib/el3_runtime/aarch64/
A Dcontext.h495 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ argument
496 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
499 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ argument
501 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
503 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ argument
505 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
/trusted-firmware-a/plat/arm/board/fvp/aarch64/
A Dfvp_helpers.S174 mov x5, #FVP_MAX_PE_PER_CPU
175 madd x0, x1, x5, x0
/trusted-firmware-a/services/spd/trusty/
A Dtrusty_helpers.S43 ldr x5, [x1, #0x18]
50 stp x4, x5, [x8, #16]
/trusted-firmware-a/lib/cpus/aarch64/
A Dwa_cve_2017_5715_bpiall.S28 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
48 mrs x5, scr_el3
275 msr scr_el3, x5
292 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]

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