| /trusted-firmware-a/include/plat/marvell/armada/common/aarch64/ |
| A D | marvell_macros.S | 50 mrs x7, id_aa64pfr0_el1
51 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
52 cmp x7, #1
84 add x7, x16, #GICD_ISPENDR
88 sub x4, x7, x16
96 ldr x4, [x7], #8
121 mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
123 ldr w8, [x7, #SNOOP_CTRL_REG]
125 mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
127 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| A D | cci_macros.S | 28 mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
30 ldr w8, [x7, #SNOOP_CTRL_REG]
32 mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
34 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/rockchip/common/include/ |
| A D | plat_macros.S | 51 mrs x7, id_aa64pfr0_el1
52 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
53 cmp x7, #1
83 add x7, x26, #GICD_ISPENDR
87 sub x4, x7, x26
95 ldr x4, [x7], #8
106 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
108 ldr w8, [x7, #SNOOP_CTRL_REG]
110 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \
112 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/include/plat/arm/common/aarch64/ |
| A D | arm_macros.S | 43 mrs x7, id_aa64pfr0_el1
44 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
45 cmp x7, #1
75 add x7, x16, #GICD_ISPENDR
79 sub x4, x7, x16
88 sub x4, x7, x16
95 ldr x4, [x7], #8
|
| A D | cci_macros.S | 26 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
28 ldr w8, [x7, #SNOOP_CTRL_REG]
30 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
32 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/hisilicon/hikey/include/ |
| A D | plat_macros.S | 49 add x7, x16, #GICD_ISPENDR
53 sub x4, x7, x16
59 ldr x4, [x7], #8
67 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
69 ldr w8, [x7, #SNOOP_CTRL_REG]
71 mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \
73 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/hisilicon/hikey960/include/ |
| A D | plat_macros.S | 49 add x7, x16, #GICD_ISPENDR
53 sub x4, x7, x16
59 ldr x4, [x7], #8
67 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
69 ldr w8, [x7, #SNOOP_CTRL_REG]
71 mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \
73 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/renesas/common/include/ |
| A D | plat_macros.S | 44 add x7, x16, #GICD_ISPENDR
48 sub x4, x7, x16
54 ldr x4, [x7], #8
76 mov_imm x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET)
77 ldr w8, [x7, #SNOOP_CTRL_REG]
79 mov_imm x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET)
80 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/mediatek/mt6795/include/ |
| A D | plat_macros.S | 41 add x7, x16, #GICD_ISPENDR
45 sub x4, x7, x16
53 ldr x4, [x7], #8
76 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
78 ldr w8, [x7, #SNOOP_CTRL_REG]
80 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
82 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/mediatek/mt8173/include/ |
| A D | plat_macros.S | 47 add x7, x16, #GICD_ISPENDR
51 sub x4, x7, x16
59 ldr x4, [x7], #8
69 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
71 ldr w8, [x7, #SNOOP_CTRL_REG]
73 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
75 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/mediatek/mt8183/include/ |
| A D | plat_macros.S | 47 add x7, x26, #GICD_ISPENDR
51 sub x4, x7, x26
59 ldr x4, [x7], #8
69 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
71 ldr w8, [x7, #SNOOP_CTRL_REG]
73 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
75 ldr w9, [x7, #SNOOP_CTRL_REG]
|
| /trusted-firmware-a/plat/qti/common/inc/aarch64/ |
| A D | plat_macros.S | 52 mrs x7, id_aa64pfr0_el1
53 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
54 cmp x7, #1
84 add x7, x26, #GICD_ISPENDR
88 sub x4, x7, x26
96 ldr x4, [x7], #8
|
| /trusted-firmware-a/plat/xilinx/versal/include/ |
| A D | plat_macros.S | 43 mrs x7, id_aa64pfr0_el1
44 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
45 cmp x7, #1
75 add x7, x16, #GICD_ISPENDR
79 sub x4, x7, x16
87 ldr x4, [x7], #8
|
| /trusted-firmware-a/lib/libc/aarch64/ |
| A D | setjmp.S | 18 mov x7, sp
26 stp x7, xzr, [x0, #JMP_CTX_SP]
37 ldp x7, xzr, [x0, #JMP_CTX_SP]
45 cmp x7, x19
56 mov sp, x7
|
| /trusted-firmware-a/plat/nxp/common/ocram/aarch64/ |
| A D | ocram.S | 29 stp x6, x7, [sp, #-16]!
42 ldp x6, x7, [x0, #16]
46 stp x6, x7, [x0, #16]
68 ldp x6, x7, [sp], #16
|
| /trusted-firmware-a/drivers/renesas/common/console/ |
| A D | rcar_console.S | 36 mov x7, x30
45 mov x30, x7
49 ret x7
|
| /trusted-firmware-a/plat/amlogic/common/include/ |
| A D | plat_macros.S | 48 add x7, x16, #GICD_ISPENDR
53 sub x4, x7, x16
61 ldr x4, [x7], #8
|
| /trusted-firmware-a/plat/nvidia/tegra/include/ |
| A D | plat_macros.S | 45 add x7, x16, #GICD_ISPENDR
49 sub x4, x7, x16
55 ldr w4, [x7], #4
|
| /trusted-firmware-a/plat/nxp/common/psci/aarch64/ |
| A D | psci_utils.S | 37 stp x6, x7, [sp, #-16]!
122 ldr x7, =SOC_CORE_RELEASE
123 cbnz x7, 3f
146 ldr x7, =SOC_CORE_RESTART
147 cbnz x7, 2f
192 ldp x6, x7, [sp], #16
219 stp x6, x7, [sp, #-16]!
273 ldp x6, x7, [sp], #16
358 ldp x6, x7, [sp], #16
583 ldp x6, x7, [sp], #16
[all …]
|
| /trusted-firmware-a/plat/imx/common/ |
| A D | lpuart_console.S | 20 mov x7, x30
29 mov x30, x7
33 ret x7
|
| A D | imx_uart_console.S | 25 mov x7, x30
34 mov x30, x7
38 ret x7
|
| /trusted-firmware-a/lib/xlat_mpu/aarch64/ |
| A D | enable_mpu.S | 21 mov x7, x0
46 tst x7, #DISABLE_DCACHE
|
| /trusted-firmware-a/bl31/aarch64/ |
| A D | crash_reporting.S | 80 mrs x7, tpidr_el3
86 cmp x7, x5
99 ldr x4, [x7], #REGSZ
222 add x7, sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0
236 ldr x4, [x7], #REGSZ
250 ldr x4, [x7]
365 str x7, [x0, #REGSZ * 7]
|
| /trusted-firmware-a/lib/cpus/aarch64/ |
| A D | wa_cve_2017_5715_bpiall.S | 29 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
58 mrs x7, elr_el3
59 stp x30, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
270 ldp x30, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
277 msr elr_el3, x7
293 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
|
| /trusted-firmware-a/drivers/cadence/uart/aarch64/ |
| A D | cdns_console.S | 72 mov x7, x30
81 mov x30, x7
85 ret x7
|