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Searched refs:ACPI_BASE_ADDRESS (Results 1 – 11 of 11) sorted by relevance

/u-boot/arch/x86/cpu/broadwell/
A Dpower_state.c68 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in power_state_get()
69 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); in power_state_get()
70 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in power_state_get()
71 ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS); in power_state_get()
72 ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS); in power_state_get()
73 ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); in power_state_get()
74 ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1)); in power_state_get()
77 ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); in power_state_get()
78 ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1)); in power_state_get()
79 ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); in power_state_get()
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A Dpch.c48 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); in broadwell_pch_early_init()
93 clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN); in pch_misc_init()
138 outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); in enable_all_gpe()
139 outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); in enable_all_gpe()
140 outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); in enable_all_gpe()
141 outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); in enable_all_gpe()
A Dnorthbridge.c31 pei_data->pmbase = ACPI_BASE_ADDRESS; in broadwell_fill_pei_data()
/u-boot/arch/x86/cpu/baytrail/
A Dacpi.c22 u16 pmbase = ACPI_BASE_ADDRESS; in acpi_create_fadt()
185 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in chipset_prev_sleep_state()
186 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in chipset_prev_sleep_state()
205 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in chipset_clear_sleep_state()
206 outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in chipset_clear_sleep_state()
/u-boot/arch/x86/include/asm/arch-braswell/
A Diomap.h41 #define ACPI_BASE_ADDRESS 0x400 macro
/u-boot/arch/x86/include/asm/arch-apollolake/
A Diomap.h20 #define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE macro
/u-boot/arch/x86/include/asm/arch-broadwell/
A Diomap.h36 #define ACPI_BASE_ADDRESS 0x1000 macro
/u-boot/arch/x86/include/asm/arch-baytrail/
A Diomap.h82 #define ACPI_BASE_ADDRESS 0x0400 macro
/u-boot/arch/x86/include/asm/acpi/
A Dlpc.asl113 IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
/u-boot/arch/x86/cpu/intel_common/
A Dacpi.c356 acpigen_write_processor(ctx, core_id, is_first ? ACPI_BASE_ADDRESS : 0, in acpi_generate_cpu_header()
/u-boot/arch/x86/include/asm/
A Dmsr-index.h82 #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14)

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