1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __MPC83XX_H__ 7 #define __MPC83XX_H__ 8 9 #include <config.h> 10 #include <asm/fsl_lbc.h> 11 #if defined(CONFIG_E300) 12 #include <asm/e300.h> 13 #endif 14 15 /* 16 * System reset offset (PowerPC standard) 17 */ 18 #define EXC_OFF_SYS_RESET 0x0100 19 #define _START_OFFSET EXC_OFF_SYS_RESET 20 21 /* 22 * IMMRBAR - Internal Memory Register Base Address 23 */ 24 #ifndef CONFIG_DEFAULT_IMMR 25 /* Default IMMR base address */ 26 #define CONFIG_DEFAULT_IMMR 0xFF400000 27 #endif 28 /* Register offset to immr */ 29 #define IMMRBAR 0x0000 30 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */ 31 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 32 33 /* 34 * LAWBAR - Local Access Window Base Address Register 35 */ 36 /* Register offset to immr */ 37 #define LBLAWBAR0 0x0020 38 #define LBLAWAR0 0x0024 39 #define LBLAWBAR1 0x0028 40 #define LBLAWAR1 0x002C 41 #define LBLAWBAR2 0x0030 42 #define LBLAWAR2 0x0034 43 #define LBLAWBAR3 0x0038 44 #define LBLAWAR3 0x003C 45 #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */ 46 47 /* 48 * SPRIDR - System Part and Revision ID Register 49 */ 50 #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 51 #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 52 53 #if defined(CONFIG_ARCH_MPC834X) 54 #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 55 #define REVID_MINOR(spridr) (spridr & 0x000000FF) 56 #else 57 #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 58 #define REVID_MINOR(spridr) (spridr & 0x0000000F) 59 #endif 60 61 #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 62 #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 63 64 #define SPR_8308 0x8100 65 #define SPR_8309 0x8110 66 #define SPR_831X_FAMILY 0x80B 67 #define SPR_8311 0x80B2 68 #define SPR_8313 0x80B0 69 #define SPR_8314 0x80B6 70 #define SPR_8315 0x80B4 71 #define SPR_832X_FAMILY 0x806 72 #define SPR_8321 0x8066 73 #define SPR_8323 0x8062 74 #define SPR_834X_FAMILY 0x803 75 #define SPR_8343 0x8036 76 #define SPR_8347_TBGA_ 0x8032 77 #define SPR_8347_PBGA_ 0x8034 78 #define SPR_8349 0x8030 79 #define SPR_836X_FAMILY 0x804 80 #define SPR_8358_TBGA_ 0x804A 81 #define SPR_8358_PBGA_ 0x804E 82 #define SPR_8360 0x8048 83 #define SPR_837X_FAMILY 0x80C 84 #define SPR_8377 0x80C6 85 #define SPR_8378 0x80C4 86 #define SPR_8379 0x80C2 87 88 /* 89 * SPCR - System Priority Configuration Register 90 */ 91 /* PCI Highest Priority Enable */ 92 #define SPCR_PCIHPE 0x10000000 93 #define SPCR_PCIHPE_SHIFT (31-3) 94 /* PCI bridge system bus request priority */ 95 #define SPCR_PCIPR 0x03000000 96 #define SPCR_PCIPR_SHIFT (31-7) 97 #define SPCR_OPT 0x00800000 /* Optimize */ 98 #define SPCR_OPT_SHIFT (31-8) 99 /* E300 PowerPC core time base unit enable */ 100 #define SPCR_TBEN 0x00400000 101 #define SPCR_TBEN_SHIFT (31-9) 102 /* E300 PowerPC Core system bus request priority */ 103 #define SPCR_COREPR 0x00300000 104 #define SPCR_COREPR_SHIFT (31-11) 105 106 #if defined(CONFIG_ARCH_MPC834X) 107 /* SPCR bits - MPC8349 specific */ 108 /* TSEC1 data priority */ 109 #define SPCR_TSEC1DP 0x00003000 110 #define SPCR_TSEC1DP_SHIFT (31-19) 111 /* TSEC1 buffer descriptor priority */ 112 #define SPCR_TSEC1BDP 0x00000C00 113 #define SPCR_TSEC1BDP_SHIFT (31-21) 114 /* TSEC1 emergency priority */ 115 #define SPCR_TSEC1EP 0x00000300 116 #define SPCR_TSEC1EP_SHIFT (31-23) 117 /* TSEC2 data priority */ 118 #define SPCR_TSEC2DP 0x00000030 119 #define SPCR_TSEC2DP_SHIFT (31-27) 120 /* TSEC2 buffer descriptor priority */ 121 #define SPCR_TSEC2BDP 0x0000000C 122 #define SPCR_TSEC2BDP_SHIFT (31-29) 123 /* TSEC2 emergency priority */ 124 #define SPCR_TSEC2EP 0x00000003 125 #define SPCR_TSEC2EP_SHIFT (31-31) 126 127 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 128 defined(CONFIG_ARCH_MPC837X) 129 /* SPCR bits - MPC8308, MPC831x and MPC837X specific */ 130 /* TSEC data priority */ 131 #define SPCR_TSECDP 0x00003000 132 #define SPCR_TSECDP_SHIFT (31-19) 133 /* TSEC buffer descriptor priority */ 134 #define SPCR_TSECBDP 0x00000C00 135 #define SPCR_TSECBDP_SHIFT (31-21) 136 /* TSEC emergency priority */ 137 #define SPCR_TSECEP 0x00000300 138 #define SPCR_TSECEP_SHIFT (31-23) 139 #endif 140 141 /* SICRL/H - System I/O Configuration Register Low/High 142 */ 143 #if defined(CONFIG_ARCH_MPC834X) 144 /* SICRL bits - MPC8349 specific */ 145 #define SICRL_LDP_A 0x80000000 146 #define SICRL_USB1 0x40000000 147 #define SICRL_USB0 0x20000000 148 #define SICRL_UART 0x0C000000 149 #define SICRL_GPIO1_A 0x02000000 150 #define SICRL_GPIO1_B 0x01000000 151 #define SICRL_GPIO1_C 0x00800000 152 #define SICRL_GPIO1_D 0x00400000 153 #define SICRL_GPIO1_E 0x00200000 154 #define SICRL_GPIO1_F 0x00180000 155 #define SICRL_GPIO1_G 0x00040000 156 #define SICRL_GPIO1_H 0x00020000 157 #define SICRL_GPIO1_I 0x00010000 158 #define SICRL_GPIO1_J 0x00008000 159 #define SICRL_GPIO1_K 0x00004000 160 #define SICRL_GPIO1_L 0x00003000 161 162 /* SICRH bits - MPC8349 specific */ 163 #define SICRH_DDR 0x80000000 164 #define SICRH_TSEC1_A 0x10000000 165 #define SICRH_TSEC1_B 0x08000000 166 #define SICRH_TSEC1_C 0x04000000 167 #define SICRH_TSEC1_D 0x02000000 168 #define SICRH_TSEC1_E 0x01000000 169 #define SICRH_TSEC1_F 0x00800000 170 #define SICRH_TSEC2_A 0x00400000 171 #define SICRH_TSEC2_B 0x00200000 172 #define SICRH_TSEC2_C 0x00100000 173 #define SICRH_TSEC2_D 0x00080000 174 #define SICRH_TSEC2_E 0x00040000 175 #define SICRH_TSEC2_F 0x00020000 176 #define SICRH_TSEC2_G 0x00010000 177 #define SICRH_TSEC2_H 0x00008000 178 #define SICRH_GPIO2_A 0x00004000 179 #define SICRH_GPIO2_B 0x00002000 180 #define SICRH_GPIO2_C 0x00001000 181 #define SICRH_GPIO2_D 0x00000800 182 #define SICRH_GPIO2_E 0x00000400 183 #define SICRH_GPIO2_F 0x00000200 184 #define SICRH_GPIO2_G 0x00000180 185 #define SICRH_GPIO2_H 0x00000060 186 #define SICRH_TSOBI1 0x00000002 187 #define SICRH_TSOBI2 0x00000001 188 189 #elif defined(CONFIG_ARCH_MPC8360) 190 /* SICRL bits - MPC8360 specific */ 191 #define SICRL_LDP_A 0xC0000000 192 #define SICRL_LCLK_1 0x10000000 193 #define SICRL_LCLK_2 0x08000000 194 #define SICRL_SRCID_A 0x03000000 195 #define SICRL_IRQ_CKSTP_A 0x00C00000 196 197 /* SICRH bits - MPC8360 specific */ 198 #define SICRH_DDR 0x80000000 199 #define SICRH_SECONDARY_DDR 0x40000000 200 #define SICRH_SDDROE 0x20000000 201 #define SICRH_IRQ3 0x10000000 202 #define SICRH_UC1EOBI 0x00000004 203 #define SICRH_UC2E1OBI 0x00000002 204 #define SICRH_UC2E2OBI 0x00000001 205 206 #elif defined(CONFIG_ARCH_MPC832X) 207 /* SICRL bits - MPC832x specific */ 208 #define SICRL_LDP_LCS_A 0x80000000 209 #define SICRL_IRQ_CKS 0x20000000 210 #define SICRL_PCI_MSRC 0x10000000 211 #define SICRL_URT_CTPR 0x06000000 212 #define SICRL_IRQ_CTPR 0x00C00000 213 214 #elif defined(CONFIG_ARCH_MPC8313) 215 /* SICRL bits - MPC8313 specific */ 216 #define SICRL_LBC 0x30000000 217 #define SICRL_UART 0x0C000000 218 #define SICRL_SPI_A 0x03000000 219 #define SICRL_SPI_B 0x00C00000 220 #define SICRL_SPI_C 0x00300000 221 #define SICRL_SPI_D 0x000C0000 222 #define SICRL_USBDR_11 0x00000C00 223 #define SICRL_USBDR_10 0x00000800 224 #define SICRL_USBDR_01 0x00000400 225 #define SICRL_USBDR_00 0x00000000 226 #define SICRL_ETSEC1_A 0x0000000C 227 #define SICRL_ETSEC2_A 0x00000003 228 229 /* SICRH bits - MPC8313 specific */ 230 #define SICRH_INTR_A 0x02000000 231 #define SICRH_INTR_B 0x00C00000 232 #define SICRH_IIC 0x00300000 233 #define SICRH_ETSEC2_B 0x000C0000 234 #define SICRH_ETSEC2_C 0x00030000 235 #define SICRH_ETSEC2_D 0x0000C000 236 #define SICRH_ETSEC2_E 0x00003000 237 #define SICRH_ETSEC2_F 0x00000C00 238 #define SICRH_ETSEC2_G 0x00000300 239 #define SICRH_ETSEC1_B 0x00000080 240 #define SICRH_ETSEC1_C 0x00000060 241 #define SICRH_GTX1_DLY 0x00000008 242 #define SICRH_GTX2_DLY 0x00000004 243 #define SICRH_TSOBI1 0x00000002 244 #define SICRH_TSOBI2 0x00000001 245 246 #elif defined(CONFIG_ARCH_MPC8315) 247 /* SICRL bits - MPC8315 specific */ 248 #define SICRL_DMA_CH0 0xc0000000 249 #define SICRL_DMA_SPI 0x30000000 250 #define SICRL_UART 0x0c000000 251 #define SICRL_IRQ4 0x02000000 252 #define SICRL_IRQ5 0x01800000 253 #define SICRL_IRQ6_7 0x00400000 254 #define SICRL_IIC1 0x00300000 255 #define SICRL_TDM 0x000c0000 256 #define SICRL_TDM_SHARED 0x00030000 257 #define SICRL_PCI_A 0x0000c000 258 #define SICRL_ELBC_A 0x00003000 259 #define SICRL_ETSEC1_A 0x000000c0 260 #define SICRL_ETSEC1_B 0x00000030 261 #define SICRL_ETSEC1_C 0x0000000c 262 #define SICRL_TSEXPOBI 0x00000001 263 264 /* SICRH bits - MPC8315 specific */ 265 #define SICRH_GPIO_0 0xc0000000 266 #define SICRH_GPIO_1 0x30000000 267 #define SICRH_GPIO_2 0x0c000000 268 #define SICRH_GPIO_3 0x03000000 269 #define SICRH_GPIO_4 0x00c00000 270 #define SICRH_GPIO_5 0x00300000 271 #define SICRH_GPIO_6 0x000c0000 272 #define SICRH_GPIO_7 0x00030000 273 #define SICRH_GPIO_8 0x0000c000 274 #define SICRH_GPIO_9 0x00003000 275 #define SICRH_GPIO_10 0x00000c00 276 #define SICRH_GPIO_11 0x00000300 277 #define SICRH_ETSEC2_A 0x000000c0 278 #define SICRH_TSOBI1 0x00000002 279 #define SICRH_TSOBI2 0x00000001 280 281 #elif defined(CONFIG_ARCH_MPC837X) 282 /* SICRL bits - MPC837X specific */ 283 #define SICRL_USB_A 0xC0000000 284 #define SICRL_USB_B 0x30000000 285 #define SICRL_USB_B_SD 0x20000000 286 #define SICRL_UART 0x0C000000 287 #define SICRL_GPIO_A 0x02000000 288 #define SICRL_GPIO_B 0x01000000 289 #define SICRL_GPIO_C 0x00800000 290 #define SICRL_GPIO_D 0x00400000 291 #define SICRL_GPIO_E 0x00200000 292 #define SICRL_GPIO_F 0x00180000 293 #define SICRL_GPIO_G 0x00040000 294 #define SICRL_GPIO_H 0x00020000 295 #define SICRL_GPIO_I 0x00010000 296 #define SICRL_GPIO_J 0x00008000 297 #define SICRL_GPIO_K 0x00004000 298 #define SICRL_GPIO_L 0x00003000 299 #define SICRL_DMA_A 0x00000800 300 #define SICRL_DMA_B 0x00000400 301 #define SICRL_DMA_C 0x00000200 302 #define SICRL_DMA_D 0x00000100 303 #define SICRL_DMA_E 0x00000080 304 #define SICRL_DMA_F 0x00000040 305 #define SICRL_DMA_G 0x00000020 306 #define SICRL_DMA_H 0x00000010 307 #define SICRL_DMA_I 0x00000008 308 #define SICRL_DMA_J 0x00000004 309 #define SICRL_LDP_A 0x00000002 310 #define SICRL_LDP_B 0x00000001 311 312 /* SICRH bits - MPC837X specific */ 313 #define SICRH_DDR 0x80000000 314 #define SICRH_TSEC1_A 0x10000000 315 #define SICRH_TSEC1_B 0x08000000 316 #define SICRH_TSEC2_A 0x00400000 317 #define SICRH_TSEC2_B 0x00200000 318 #define SICRH_TSEC2_C 0x00100000 319 #define SICRH_TSEC2_D 0x00080000 320 #define SICRH_TSEC2_E 0x00040000 321 #define SICRH_TMR 0x00010000 322 #define SICRH_GPIO2_A 0x00008000 323 #define SICRH_GPIO2_B 0x00004000 324 #define SICRH_GPIO2_C 0x00002000 325 #define SICRH_GPIO2_D 0x00001000 326 #define SICRH_GPIO2_E 0x00000C00 327 #define SICRH_GPIO2_E_SD 0x00000800 328 #define SICRH_GPIO2_F 0x00000300 329 #define SICRH_GPIO2_G 0x000000C0 330 #define SICRH_GPIO2_H 0x00000030 331 #define SICRH_SPI 0x00000003 332 #define SICRH_SPI_SD 0x00000001 333 334 #elif defined(CONFIG_ARCH_MPC8308) 335 /* SICRL bits - MPC8308 specific */ 336 #define SICRL_SPI_PF0 (0 << 28) 337 #define SICRL_SPI_PF1 (1 << 28) 338 #define SICRL_SPI_PF3 (3 << 28) 339 #define SICRL_UART_PF0 (0 << 26) 340 #define SICRL_UART_PF1 (1 << 26) 341 #define SICRL_UART_PF3 (3 << 26) 342 #define SICRL_IRQ_PF0 (0 << 24) 343 #define SICRL_IRQ_PF1 (1 << 24) 344 #define SICRL_I2C2_PF0 (0 << 20) 345 #define SICRL_I2C2_PF1 (1 << 20) 346 #define SICRL_ETSEC1_TX_CLK (0 << 6) 347 #define SICRL_ETSEC1_GTX_CLK125 (1 << 6) 348 349 /* SICRH bits - MPC8308 specific */ 350 #define SICRH_ESDHC_A_SD (0 << 30) 351 #define SICRH_ESDHC_A_GTM (1 << 30) 352 #define SICRH_ESDHC_A_GPIO (3 << 30) 353 #define SICRH_ESDHC_B_SD (0 << 28) 354 #define SICRH_ESDHC_B_GTM (1 << 28) 355 #define SICRH_ESDHC_B_GPIO (3 << 28) 356 #define SICRH_ESDHC_C_SD (0 << 26) 357 #define SICRH_ESDHC_C_GTM (1 << 26) 358 #define SICRH_ESDHC_C_GPIO (3 << 26) 359 #define SICRH_GPIO_A_GPIO (0 << 24) 360 #define SICRH_GPIO_A_TSEC2 (1 << 24) 361 #define SICRH_GPIO_B_GPIO (0 << 22) 362 #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) 363 #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) 364 #define SICRH_IEEE1588_A_TMR (1 << 20) 365 #define SICRH_IEEE1588_A_GPIO (3 << 20) 366 #define SICRH_USB (1 << 18) 367 #define SICRH_GTM_GTM (1 << 16) 368 #define SICRH_GTM_GPIO (3 << 16) 369 #define SICRH_IEEE1588_B_TMR (1 << 14) 370 #define SICRH_IEEE1588_B_GPIO (3 << 14) 371 #define SICRH_ETSEC2_CRS (1 << 12) 372 #define SICRH_ETSEC2_GPIO (3 << 12) 373 #define SICRH_GPIOSEL_0 (0 << 8) 374 #define SICRH_GPIOSEL_1 (1 << 8) 375 #define SICRH_TMROBI_V3P3 (0 << 4) 376 #define SICRH_TMROBI_V2P5 (1 << 4) 377 #define SICRH_TSOBI1_V3P3 (0 << 1) 378 #define SICRH_TSOBI1_V2P5 (1 << 1) 379 #define SICRH_TSOBI2_V3P3 (0 << 0) 380 #define SICRH_TSOBI2_V2P5 (1 << 0) 381 382 #elif defined(CONFIG_ARCH_MPC8309) 383 /* SICR_1 */ 384 #define SICR_1_UART1_UART1S (0 << (30-2)) 385 #define SICR_1_UART1_UART1RTS (1 << (30-2)) 386 #define SICR_1_I2C_I2C (0 << (30-4)) 387 #define SICR_1_I2C_CKSTOP (1 << (30-4)) 388 #define SICR_1_IRQ_A_IRQ (0 << (30-6)) 389 #define SICR_1_IRQ_A_MCP (1 << (30-6)) 390 #define SICR_1_IRQ_B_IRQ (0 << (30-8)) 391 #define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) 392 #define SICR_1_GPIO_A_GPIO (0 << (30-10)) 393 #define SICR_1_GPIO_A_SD (2 << (30-10)) 394 #define SICR_1_GPIO_A_DDR (3 << (30-10)) 395 #define SICR_1_GPIO_B_GPIO (0 << (30-12)) 396 #define SICR_1_GPIO_B_SD (2 << (30-12)) 397 #define SICR_1_GPIO_B_QE (3 << (30-12)) 398 #define SICR_1_GPIO_C_GPIO (0 << (30-14)) 399 #define SICR_1_GPIO_C_CAN (1 << (30-14)) 400 #define SICR_1_GPIO_C_DDR (2 << (30-14)) 401 #define SICR_1_GPIO_C_LCS (3 << (30-14)) 402 #define SICR_1_GPIO_D_GPIO (0 << (30-16)) 403 #define SICR_1_GPIO_D_CAN (1 << (30-16)) 404 #define SICR_1_GPIO_D_DDR (2 << (30-16)) 405 #define SICR_1_GPIO_D_LCS (3 << (30-16)) 406 #define SICR_1_GPIO_E_GPIO (0 << (30-18)) 407 #define SICR_1_GPIO_E_CAN (1 << (30-18)) 408 #define SICR_1_GPIO_E_DDR (2 << (30-18)) 409 #define SICR_1_GPIO_E_LCS (3 << (30-18)) 410 #define SICR_1_GPIO_F_GPIO (0 << (30-20)) 411 #define SICR_1_GPIO_F_CAN (1 << (30-20)) 412 #define SICR_1_GPIO_F_CK (2 << (30-20)) 413 #define SICR_1_USB_A_USBDR (0 << (30-22)) 414 #define SICR_1_USB_A_UART2S (1 << (30-22)) 415 #define SICR_1_USB_B_USBDR (0 << (30-24)) 416 #define SICR_1_USB_B_UART2S (1 << (30-24)) 417 #define SICR_1_USB_B_UART2RTS (2 << (30-24)) 418 #define SICR_1_USB_C_USBDR (0 << (30-26)) 419 #define SICR_1_USB_C_QE_EXT (3 << (30-26)) 420 #define SICR_1_FEC1_FEC1 (0 << (30-28)) 421 #define SICR_1_FEC1_GTM (1 << (30-28)) 422 #define SICR_1_FEC1_GPIO (2 << (30-28)) 423 #define SICR_1_FEC2_FEC2 (0 << (30-30)) 424 #define SICR_1_FEC2_GTM (1 << (30-30)) 425 #define SICR_1_FEC2_GPIO (2 << (30-30)) 426 /* SICR_2 */ 427 #define SICR_2_FEC3_FEC3 (0 << (30-0)) 428 #define SICR_2_FEC3_TMR (1 << (30-0)) 429 #define SICR_2_FEC3_GPIO (2 << (30-0)) 430 #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) 431 #define SICR_2_HDLC1_A_GPIO (1 << (30-2)) 432 #define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) 433 #define SICR_2_ELBC_A_LA (0 << (30-4)) 434 #define SICR_2_ELBC_B_LCLK (0 << (30-6)) 435 #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) 436 #define SICR_2_HDLC2_A_GPIO (0 << (30-8)) 437 #define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) 438 /* bits 10-11 unused */ 439 #define SICR_2_USB_D_USBDR (0 << (30-12)) 440 #define SICR_2_USB_D_GPIO (2 << (30-12)) 441 #define SICR_2_USB_D_QE_BRG (3 << (30-12)) 442 #define SICR_2_PCI_PCI (0 << (30-14)) 443 #define SICR_2_PCI_CPCI_HS (2 << (30-14)) 444 #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) 445 #define SICR_2_HDLC1_B_GPIO (1 << (30-16)) 446 #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) 447 #define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) 448 #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) 449 #define SICR_2_HDLC1_C_GPIO (1 << (30-18)) 450 #define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) 451 #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) 452 #define SICR_2_HDLC2_B_GPIO (1 << (30-20)) 453 #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) 454 #define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) 455 #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) 456 #define SICR_2_HDLC2_C_GPIO (1 << (30-22)) 457 #define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) 458 #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) 459 #define SICR_2_QUIESCE_B (0 << (30-24)) 460 461 #endif 462 463 /* 464 * SWCRR - System Watchdog Control Register 465 */ 466 /* Register offset to immr */ 467 #define SWCRR 0x0204 468 /* Software Watchdog Time Count */ 469 #define SWCRR_SWTC 0xFFFF0000 470 /* Watchdog Enable bit */ 471 #define SWCRR_SWEN 0x00000004 472 /* Software Watchdog Reset/Interrupt Select bit */ 473 #define SWCRR_SWRI 0x00000002 474 /* Software Watchdog Counter Prescale bit */ 475 #define SWCRR_SWPR 0x00000001 476 #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \ 477 SWCRR_SWRI | SWCRR_SWPR)) 478 479 /* 480 * SWCNR - System Watchdog Counter Register 481 */ 482 /* Register offset to immr */ 483 #define SWCNR 0x0208 484 /* Software Watchdog Count mask */ 485 #define SWCNR_SWCN 0x0000FFFF 486 #define SWCNR_RES ~(SWCNR_SWCN) 487 488 /* 489 * SWSRR - System Watchdog Service Register 490 */ 491 /* Register offset to immr */ 492 #define SWSRR 0x020E 493 494 /* 495 * ACR - Arbiter Configuration Register 496 */ 497 #define ACR_COREDIS 0x10000000 /* Core disable */ 498 #define ACR_COREDIS_SHIFT (31-7) 499 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 500 #define ACR_PIPE_DEP_SHIFT (31-15) 501 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 502 #define ACR_PCI_RPTCNT_SHIFT (31-19) 503 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 504 #define ACR_RPTCNT_SHIFT (31-23) 505 #define ACR_APARK 0x00000030 /* Address parking */ 506 #define ACR_APARK_SHIFT (31-27) 507 #define ACR_PARKM 0x0000000F /* Parking master */ 508 #define ACR_PARKM_SHIFT (31-31) 509 510 /* 511 * ATR - Arbiter Timers Register 512 */ 513 #define ATR_DTO 0x00FF0000 /* Data time out */ 514 #define ATR_DTO_SHIFT 16 515 #define ATR_ATO 0x000000FF /* Address time out */ 516 #define ATR_ATO_SHIFT 0 517 518 /* 519 * AER - Arbiter Event Register 520 */ 521 #define AER_ETEA 0x00000020 /* Transfer error */ 522 /* Reserved transfer type */ 523 #define AER_RES 0x00000010 524 /* External control word transfer type */ 525 #define AER_ECW 0x00000008 526 /* Address Only transfer type */ 527 #define AER_AO 0x00000004 528 #define AER_DTO 0x00000002 /* Data time out */ 529 #define AER_ATO 0x00000001 /* Address time out */ 530 531 /* 532 * AEATR - Arbiter Event Address Register 533 */ 534 #define AEATR_EVENT 0x07000000 /* Event type */ 535 #define AEATR_EVENT_SHIFT 24 536 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 537 #define AEATR_MSTR_ID_SHIFT 16 538 #define AEATR_TBST 0x00000800 /* Transfer burst */ 539 #define AEATR_TBST_SHIFT 11 540 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 541 #define AEATR_TSIZE_SHIFT 8 542 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 543 #define AEATR_TTYPE_SHIFT 0 544 545 /* 546 * HRCWL - Hard Reset Configuration Word Low 547 */ 548 #define HRCWL_LBIUCM 0x80000000 549 #define HRCWL_LBIUCM_SHIFT 31 550 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 551 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 552 553 #define HRCWL_DDRCM 0x40000000 554 #define HRCWL_DDRCM_SHIFT 30 555 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 556 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 557 558 #define HRCWL_SPMF 0x0f000000 559 #define HRCWL_SPMF_SHIFT 24 560 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 561 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 562 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 563 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 564 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 565 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 566 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 567 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 568 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 569 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 570 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 571 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 572 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 573 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 574 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 575 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 576 577 #define HRCWL_VCO_BYPASS 0x00000000 578 #define HRCWL_VCO_1X2 0x00000000 579 #define HRCWL_VCO_1X4 0x00200000 580 #define HRCWL_VCO_1X8 0x00400000 581 582 #define HRCWL_COREPLL 0x007F0000 583 #define HRCWL_COREPLL_SHIFT 16 584 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 585 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 586 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 587 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 588 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 589 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 590 591 #if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X) 592 #define HRCWL_CEVCOD 0x000000C0 593 #define HRCWL_CEVCOD_SHIFT 6 594 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 595 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 596 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 597 598 #define HRCWL_CEPDF 0x00000020 599 #define HRCWL_CEPDF_SHIFT 5 600 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 601 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 602 603 #define HRCWL_CEPMF 0x0000001F 604 #define HRCWL_CEPMF_SHIFT 0 605 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 606 #define HRCWL_CE_TO_PLL_1X2 0x00000002 607 #define HRCWL_CE_TO_PLL_1X3 0x00000003 608 #define HRCWL_CE_TO_PLL_1X4 0x00000004 609 #define HRCWL_CE_TO_PLL_1X5 0x00000005 610 #define HRCWL_CE_TO_PLL_1X6 0x00000006 611 #define HRCWL_CE_TO_PLL_1X7 0x00000007 612 #define HRCWL_CE_TO_PLL_1X8 0x00000008 613 #define HRCWL_CE_TO_PLL_1X9 0x00000009 614 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 615 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 616 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 617 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 618 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 619 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 620 #define HRCWL_CE_TO_PLL_1X16 0x00000010 621 #define HRCWL_CE_TO_PLL_1X17 0x00000011 622 #define HRCWL_CE_TO_PLL_1X18 0x00000012 623 #define HRCWL_CE_TO_PLL_1X19 0x00000013 624 #define HRCWL_CE_TO_PLL_1X20 0x00000014 625 #define HRCWL_CE_TO_PLL_1X21 0x00000015 626 #define HRCWL_CE_TO_PLL_1X22 0x00000016 627 #define HRCWL_CE_TO_PLL_1X23 0x00000017 628 #define HRCWL_CE_TO_PLL_1X24 0x00000018 629 #define HRCWL_CE_TO_PLL_1X25 0x00000019 630 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 631 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 632 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 633 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 634 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 635 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 636 637 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) 638 #define HRCWL_SVCOD 0x30000000 639 #define HRCWL_SVCOD_SHIFT 28 640 #define HRCWL_SVCOD_DIV_2 0x00000000 641 #define HRCWL_SVCOD_DIV_4 0x10000000 642 #define HRCWL_SVCOD_DIV_8 0x20000000 643 #define HRCWL_SVCOD_DIV_1 0x30000000 644 645 #elif defined(CONFIG_ARCH_MPC837X) 646 #define HRCWL_SVCOD 0x30000000 647 #define HRCWL_SVCOD_SHIFT 28 648 #define HRCWL_SVCOD_DIV_4 0x00000000 649 #define HRCWL_SVCOD_DIV_8 0x10000000 650 #define HRCWL_SVCOD_DIV_2 0x20000000 651 #define HRCWL_SVCOD_DIV_1 0x30000000 652 #elif defined(CONFIG_ARCH_MPC8309) 653 654 #define HRCWL_CEVCOD 0x000000C0 655 #define HRCWL_CEVCOD_SHIFT 6 656 /* 657 * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 658 * these are different than with 8360, 832x 659 */ 660 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 661 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 662 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 663 664 #define HRCWL_CEPDF 0x00000020 665 #define HRCWL_CEPDF_SHIFT 5 666 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 667 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 668 669 #define HRCWL_CEPMF 0x0000001F 670 #define HRCWL_CEPMF_SHIFT 0 671 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 672 #define HRCWL_CE_TO_PLL_1X2 0x00000002 673 #define HRCWL_CE_TO_PLL_1X3 0x00000003 674 #define HRCWL_CE_TO_PLL_1X4 0x00000004 675 #define HRCWL_CE_TO_PLL_1X5 0x00000005 676 #define HRCWL_CE_TO_PLL_1X6 0x00000006 677 #define HRCWL_CE_TO_PLL_1X7 0x00000007 678 #define HRCWL_CE_TO_PLL_1X8 0x00000008 679 #define HRCWL_CE_TO_PLL_1X9 0x00000009 680 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 681 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 682 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 683 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 684 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 685 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 686 #define HRCWL_CE_TO_PLL_1X16 0x00000010 687 #define HRCWL_CE_TO_PLL_1X17 0x00000011 688 #define HRCWL_CE_TO_PLL_1X18 0x00000012 689 #define HRCWL_CE_TO_PLL_1X19 0x00000013 690 #define HRCWL_CE_TO_PLL_1X20 0x00000014 691 #define HRCWL_CE_TO_PLL_1X21 0x00000015 692 #define HRCWL_CE_TO_PLL_1X22 0x00000016 693 #define HRCWL_CE_TO_PLL_1X23 0x00000017 694 #define HRCWL_CE_TO_PLL_1X24 0x00000018 695 #define HRCWL_CE_TO_PLL_1X25 0x00000019 696 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 697 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 698 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 699 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 700 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 701 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 702 703 #define HRCWL_SVCOD 0x30000000 704 #define HRCWL_SVCOD_SHIFT 28 705 #define HRCWL_SVCOD_DIV_2 0x00000000 706 #define HRCWL_SVCOD_DIV_4 0x10000000 707 #define HRCWL_SVCOD_DIV_8 0x20000000 708 #define HRCWL_SVCOD_DIV_1 0x30000000 709 #endif 710 711 /* 712 * HRCWH - Hardware Reset Configuration Word High 713 */ 714 #define HRCWH_PCI_HOST 0x80000000 715 #define HRCWH_PCI_HOST_SHIFT 31 716 #define HRCWH_PCI_AGENT 0x00000000 717 718 #if defined(CONFIG_ARCH_MPC834X) 719 #define HRCWH_32_BIT_PCI 0x00000000 720 #define HRCWH_64_BIT_PCI 0x40000000 721 #endif 722 723 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 724 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 725 726 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 727 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 728 729 #if defined(CONFIG_ARCH_MPC834X) 730 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 731 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 732 733 #elif defined(CONFIG_ARCH_MPC8360) 734 #define HRCWH_PCICKDRV_DISABLE 0x00000000 735 #define HRCWH_PCICKDRV_ENABLE 0x10000000 736 #endif 737 738 #define HRCWH_CORE_DISABLE 0x08000000 739 #define HRCWH_CORE_ENABLE 0x00000000 740 741 #define HRCWH_FROM_0X00000100 0x00000000 742 #define HRCWH_FROM_0XFFF00100 0x04000000 743 744 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 745 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 746 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 747 748 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 749 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 750 751 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 752 #define HRCWH_ROM_LOC_PCI1 0x00100000 753 #if defined(CONFIG_ARCH_MPC834X) 754 #define HRCWH_ROM_LOC_PCI2 0x00200000 755 #endif 756 #if defined(CONFIG_ARCH_MPC837X) 757 #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 758 #endif 759 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 760 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 761 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 762 763 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 764 defined(CONFIG_ARCH_MPC837X) 765 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 766 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 767 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 768 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 769 770 #define HRCWH_RL_EXT_LEGACY 0x00000000 771 #define HRCWH_RL_EXT_NAND 0x00040000 772 773 #define HRCWH_TSEC1M_MASK 0x0000E000 774 #define HRCWH_TSEC1M_IN_MII 0x00000000 775 #define HRCWH_TSEC1M_IN_RMII 0x00002000 776 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 777 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 778 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 779 780 #define HRCWH_TSEC2M_MASK 0x00001C00 781 #define HRCWH_TSEC2M_IN_MII 0x00000000 782 #define HRCWH_TSEC2M_IN_RMII 0x00000400 783 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 784 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 785 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 786 #endif 787 788 #if defined(CONFIG_ARCH_MPC834X) 789 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 790 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 791 #define HRCWH_TSEC1M_IN_GMII 0x00008000 792 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 793 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 794 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 795 #define HRCWH_TSEC2M_IN_GMII 0x00002000 796 #define HRCWH_TSEC2M_IN_TBI 0x00003000 797 #endif 798 799 #if defined(CONFIG_ARCH_MPC8360) 800 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 801 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 802 #endif 803 804 #define HRCWH_BIG_ENDIAN 0x00000000 805 #define HRCWH_LITTLE_ENDIAN 0x00000008 806 807 #define HRCWH_LALE_NORMAL 0x00000000 808 #define HRCWH_LALE_EARLY 0x00000004 809 810 #define HRCWH_LDP_SET 0x00000000 811 #define HRCWH_LDP_CLEAR 0x00000002 812 813 /* 814 * RSR - Reset Status Register 815 */ 816 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ 817 defined(CONFIG_ARCH_MPC837X) 818 #define RSR_RSTSRC 0xF0000000 /* Reset source */ 819 #define RSR_RSTSRC_SHIFT 28 820 #else 821 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 822 #define RSR_RSTSRC_SHIFT 29 823 #endif 824 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 825 #define RSR_BSF_SHIFT 16 826 /* software soft reset */ 827 #define RSR_SWSR 0x00002000 828 #define RSR_SWSR_SHIFT 13 829 /* software hard reset */ 830 #define RSR_SWHR 0x00001000 831 #define RSR_SWHR_SHIFT 12 832 #define RSR_JHRS 0x00000200 /* jtag hreset */ 833 #define RSR_JHRS_SHIFT 9 834 /* jtag sreset status */ 835 #define RSR_JSRS 0x00000100 836 #define RSR_JSRS_SHIFT 8 837 /* checkstop reset status */ 838 #define RSR_CSHR 0x00000010 839 #define RSR_CSHR_SHIFT 4 840 /* software watchdog reset status */ 841 #define RSR_SWRS 0x00000008 842 #define RSR_SWRS_SHIFT 3 843 /* bus monitop reset status */ 844 #define RSR_BMRS 0x00000004 845 #define RSR_BMRS_SHIFT 2 846 #define RSR_SRS 0x00000002 /* soft reset status */ 847 #define RSR_SRS_SHIFT 1 848 #define RSR_HRS 0x00000001 /* hard reset status */ 849 #define RSR_HRS_SHIFT 0 850 #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \ 851 RSR_SWHR | RSR_JHRS | \ 852 RSR_JSRS | RSR_CSHR | \ 853 RSR_SWRS | RSR_BMRS | \ 854 RSR_SRS | RSR_HRS)) 855 /* 856 * RMR - Reset Mode Register 857 */ 858 /* checkstop reset enable */ 859 #define RMR_CSRE 0x00000001 860 #define RMR_CSRE_SHIFT 0 861 #define RMR_RES ~(RMR_CSRE) 862 863 /* 864 * RCR - Reset Control Register 865 */ 866 /* software hard reset */ 867 #define RCR_SWHR 0x00000002 868 /* software soft reset */ 869 #define RCR_SWSR 0x00000001 870 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 871 872 /* 873 * RCER - Reset Control Enable Register 874 */ 875 /* software hard reset */ 876 #define RCER_CRE 0x00000001 877 #define RCER_RES ~(RCER_CRE) 878 879 /* 880 * SPMR - System PLL Mode Register 881 */ 882 #define SPMR_LBIUCM 0x80000000 883 #define SPMR_LBIUCM_SHIFT 31 884 #define SPMR_DDRCM 0x40000000 885 #define SPMR_DDRCM_SHIFT 30 886 #define SPMR_SPMF 0x0F000000 887 #define SPMR_SPMF_SHIFT 24 888 #define SPMR_CKID 0x00800000 889 #define SPMR_CKID_SHIFT 23 890 #define SPMR_COREPLL 0x007F0000 891 #define SPMR_COREPLL_SHIFT 16 892 #define SPMR_CEVCOD 0x000000C0 893 #define SPMR_CEVCOD_SHIFT 6 894 #define SPMR_CEPDF 0x00000020 895 #define SPMR_CEPDF_SHIFT 5 896 #define SPMR_CEPMF 0x0000001F 897 #define SPMR_CEPMF_SHIFT 0 898 899 /* 900 * OCCR - Output Clock Control Register 901 */ 902 #define OCCR_PCICOE0 0x80000000 903 #define OCCR_PCICOE1 0x40000000 904 #define OCCR_PCICOE2 0x20000000 905 #define OCCR_PCICOE3 0x10000000 906 #define OCCR_PCICOE4 0x08000000 907 #define OCCR_PCICOE5 0x04000000 908 #define OCCR_PCICOE6 0x02000000 909 #define OCCR_PCICOE7 0x01000000 910 #define OCCR_PCICD0 0x00800000 911 #define OCCR_PCICD1 0x00400000 912 #define OCCR_PCICD2 0x00200000 913 #define OCCR_PCICD3 0x00100000 914 #define OCCR_PCICD4 0x00080000 915 #define OCCR_PCICD5 0x00040000 916 #define OCCR_PCICD6 0x00020000 917 #define OCCR_PCICD7 0x00010000 918 #define OCCR_PCI1CR 0x00000002 919 #define OCCR_PCI2CR 0x00000001 920 #define OCCR_PCICR OCCR_PCI1CR 921 922 /* 923 * SCCR - System Clock Control Register 924 */ 925 #define SCCR_ENCCM 0x03000000 926 #define SCCR_ENCCM_SHIFT 24 927 #define SCCR_ENCCM_0 0x00000000 928 #define SCCR_ENCCM_1 0x01000000 929 #define SCCR_ENCCM_2 0x02000000 930 #define SCCR_ENCCM_3 0x03000000 931 932 #define SCCR_PCICM 0x00010000 933 #define SCCR_PCICM_SHIFT 16 934 935 #if defined(CONFIG_ARCH_MPC834X) 936 /* SCCR bits - MPC834X specific */ 937 #define SCCR_TSEC1CM 0xc0000000 938 #define SCCR_TSEC1CM_SHIFT 30 939 #define SCCR_TSEC1CM_0 0x00000000 940 #define SCCR_TSEC1CM_1 0x40000000 941 #define SCCR_TSEC1CM_2 0x80000000 942 #define SCCR_TSEC1CM_3 0xC0000000 943 944 #define SCCR_TSEC2CM 0x30000000 945 #define SCCR_TSEC2CM_SHIFT 28 946 #define SCCR_TSEC2CM_0 0x00000000 947 #define SCCR_TSEC2CM_1 0x10000000 948 #define SCCR_TSEC2CM_2 0x20000000 949 #define SCCR_TSEC2CM_3 0x30000000 950 951 /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 952 #define SCCR_USBMPHCM 0x00c00000 953 #define SCCR_USBMPHCM_SHIFT 22 954 #define SCCR_USBDRCM 0x00300000 955 #define SCCR_USBDRCM_SHIFT 20 956 #define SCCR_USBCM 0x00f00000 957 #define SCCR_USBCM_SHIFT 20 958 #define SCCR_USBCM_0 0x00000000 959 #define SCCR_USBCM_1 0x00500000 960 #define SCCR_USBCM_2 0x00A00000 961 #define SCCR_USBCM_3 0x00F00000 962 963 #elif defined(CONFIG_ARCH_MPC8313) 964 /* TSEC1 bits are for TSEC2 as well */ 965 #define SCCR_TSEC1CM 0xc0000000 966 #define SCCR_TSEC1CM_SHIFT 30 967 #define SCCR_TSEC1CM_0 0x00000000 968 #define SCCR_TSEC1CM_1 0x40000000 969 #define SCCR_TSEC1CM_2 0x80000000 970 #define SCCR_TSEC1CM_3 0xC0000000 971 972 #define SCCR_TSEC1ON 0x20000000 973 #define SCCR_TSEC1ON_SHIFT 29 974 #define SCCR_TSEC2ON 0x10000000 975 #define SCCR_TSEC2ON_SHIFT 28 976 977 #define SCCR_USBDRCM 0x00300000 978 #define SCCR_USBDRCM_SHIFT 20 979 #define SCCR_USBDRCM_0 0x00000000 980 #define SCCR_USBDRCM_1 0x00100000 981 #define SCCR_USBDRCM_2 0x00200000 982 #define SCCR_USBDRCM_3 0x00300000 983 984 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) 985 /* SCCR bits - MPC8315/MPC8308 specific */ 986 #define SCCR_TSEC1CM 0xc0000000 987 #define SCCR_TSEC1CM_SHIFT 30 988 #define SCCR_TSEC1CM_0 0x00000000 989 #define SCCR_TSEC1CM_1 0x40000000 990 #define SCCR_TSEC1CM_2 0x80000000 991 #define SCCR_TSEC1CM_3 0xC0000000 992 993 #define SCCR_TSEC2CM 0x30000000 994 #define SCCR_TSEC2CM_SHIFT 28 995 #define SCCR_TSEC2CM_0 0x00000000 996 #define SCCR_TSEC2CM_1 0x10000000 997 #define SCCR_TSEC2CM_2 0x20000000 998 #define SCCR_TSEC2CM_3 0x30000000 999 1000 #define SCCR_SDHCCM 0x0c000000 1001 #define SCCR_SDHCCM_SHIFT 26 1002 #define SCCR_SDHCCM_0 0x00000000 1003 #define SCCR_SDHCCM_1 0x04000000 1004 #define SCCR_SDHCCM_2 0x08000000 1005 #define SCCR_SDHCCM_3 0x0c000000 1006 1007 #define SCCR_USBDRCM 0x00c00000 1008 #define SCCR_USBDRCM_SHIFT 22 1009 #define SCCR_USBDRCM_0 0x00000000 1010 #define SCCR_USBDRCM_1 0x00400000 1011 #define SCCR_USBDRCM_2 0x00800000 1012 #define SCCR_USBDRCM_3 0x00c00000 1013 1014 #define SCCR_SATA1CM 0x00003000 1015 #define SCCR_SATA1CM_SHIFT 12 1016 #define SCCR_SATACM 0x00003c00 1017 #define SCCR_SATACM_SHIFT 10 1018 #define SCCR_SATACM_0 0x00000000 1019 #define SCCR_SATACM_1 0x00001400 1020 #define SCCR_SATACM_2 0x00002800 1021 #define SCCR_SATACM_3 0x00003c00 1022 1023 #define SCCR_TDMCM 0x00000030 1024 #define SCCR_TDMCM_SHIFT 4 1025 #define SCCR_TDMCM_0 0x00000000 1026 #define SCCR_TDMCM_1 0x00000010 1027 #define SCCR_TDMCM_2 0x00000020 1028 #define SCCR_TDMCM_3 0x00000030 1029 1030 #elif defined(CONFIG_ARCH_MPC837X) 1031 /* SCCR bits - MPC837X specific */ 1032 #define SCCR_TSEC1CM 0xc0000000 1033 #define SCCR_TSEC1CM_SHIFT 30 1034 #define SCCR_TSEC1CM_0 0x00000000 1035 #define SCCR_TSEC1CM_1 0x40000000 1036 #define SCCR_TSEC1CM_2 0x80000000 1037 #define SCCR_TSEC1CM_3 0xC0000000 1038 1039 #define SCCR_TSEC2CM 0x30000000 1040 #define SCCR_TSEC2CM_SHIFT 28 1041 #define SCCR_TSEC2CM_0 0x00000000 1042 #define SCCR_TSEC2CM_1 0x10000000 1043 #define SCCR_TSEC2CM_2 0x20000000 1044 #define SCCR_TSEC2CM_3 0x30000000 1045 1046 #define SCCR_SDHCCM 0x0c000000 1047 #define SCCR_SDHCCM_SHIFT 26 1048 #define SCCR_SDHCCM_0 0x00000000 1049 #define SCCR_SDHCCM_1 0x04000000 1050 #define SCCR_SDHCCM_2 0x08000000 1051 #define SCCR_SDHCCM_3 0x0c000000 1052 1053 #define SCCR_USBDRCM 0x00c00000 1054 #define SCCR_USBDRCM_SHIFT 22 1055 #define SCCR_USBDRCM_0 0x00000000 1056 #define SCCR_USBDRCM_1 0x00400000 1057 #define SCCR_USBDRCM_2 0x00800000 1058 #define SCCR_USBDRCM_3 0x00c00000 1059 1060 /* All of the four SATA controllers must have the same clock ratio */ 1061 #define SCCR_SATA1CM 0x000000c0 1062 #define SCCR_SATA1CM_SHIFT 6 1063 #define SCCR_SATACM 0x000000ff 1064 #define SCCR_SATACM_SHIFT 0 1065 #define SCCR_SATACM_0 0x00000000 1066 #define SCCR_SATACM_1 0x00000055 1067 #define SCCR_SATACM_2 0x000000aa 1068 #define SCCR_SATACM_3 0x000000ff 1069 #elif defined(CONFIG_ARCH_MPC8309) 1070 /* SCCR bits - MPC8309 specific */ 1071 #define SCCR_SDHCCM 0x0c000000 1072 #define SCCR_SDHCCM_SHIFT 26 1073 #define SCCR_SDHCCM_0 0x00000000 1074 #define SCCR_SDHCCM_1 0x04000000 1075 #define SCCR_SDHCCM_2 0x08000000 1076 #define SCCR_SDHCCM_3 0x0c000000 1077 1078 #define SCCR_USBDRCM 0x00c00000 1079 #define SCCR_USBDRCM_SHIFT 22 1080 #define SCCR_USBDRCM_0 0x00000000 1081 #define SCCR_USBDRCM_1 0x00400000 1082 #define SCCR_USBDRCM_2 0x00800000 1083 #define SCCR_USBDRCM_3 0x00c00000 1084 #endif 1085 1086 #define SCCR_PCIEXP1CM 0x00300000 1087 #define SCCR_PCIEXP1CM_SHIFT 20 1088 #define SCCR_PCIEXP1CM_0 0x00000000 1089 #define SCCR_PCIEXP1CM_1 0x00100000 1090 #define SCCR_PCIEXP1CM_2 0x00200000 1091 #define SCCR_PCIEXP1CM_3 0x00300000 1092 1093 #define SCCR_PCIEXP2CM 0x000c0000 1094 #define SCCR_PCIEXP2CM_SHIFT 18 1095 #define SCCR_PCIEXP2CM_0 0x00000000 1096 #define SCCR_PCIEXP2CM_1 0x00040000 1097 #define SCCR_PCIEXP2CM_2 0x00080000 1098 #define SCCR_PCIEXP2CM_3 0x000c0000 1099 1100 /* 1101 * CSn_BDNS - Chip Select memory Bounds Register 1102 */ 1103 #define CSBNDS_SA 0x00FF0000 1104 #define CSBNDS_SA_SHIFT 8 1105 #define CSBNDS_EA 0x000000FF 1106 #define CSBNDS_EA_SHIFT 24 1107 1108 #ifndef CONFIG_MPC83XX_SDRAM 1109 1110 /* 1111 * CSn_CONFIG - Chip Select Configuration Register 1112 */ 1113 #define CSCONFIG_EN 0x80000000 1114 #define CSCONFIG_AP 0x00800000 1115 #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) 1116 #define CSCONFIG_ODT_RD_NEVER 0x00000000 1117 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 1118 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 1119 #define CSCONFIG_ODT_RD_ALL 0x00400000 1120 #define CSCONFIG_ODT_WR_NEVER 0x00000000 1121 #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 1122 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 1123 #define CSCONFIG_ODT_WR_ALL 0x00040000 1124 #elif defined(CONFIG_ARCH_MPC832X) 1125 #define CSCONFIG_ODT_RD_CFG 0x00400000 1126 #define CSCONFIG_ODT_WR_CFG 0x00040000 1127 #elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X) 1128 #define CSCONFIG_ODT_RD_NEVER 0x00000000 1129 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 1130 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 1131 #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000 1132 #define CSCONFIG_ODT_RD_ALL 0x00400000 1133 #define CSCONFIG_ODT_WR_NEVER 0x00000000 1134 #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 1135 #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 1136 #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000 1137 #define CSCONFIG_ODT_WR_ALL 0x00040000 1138 #endif 1139 #define CSCONFIG_BANK_BIT_3 0x00004000 1140 #define CSCONFIG_ROW_BIT 0x00000700 1141 #define CSCONFIG_ROW_BIT_12 0x00000000 1142 #define CSCONFIG_ROW_BIT_13 0x00000100 1143 #define CSCONFIG_ROW_BIT_14 0x00000200 1144 #define CSCONFIG_COL_BIT 0x00000007 1145 #define CSCONFIG_COL_BIT_8 0x00000000 1146 #define CSCONFIG_COL_BIT_9 0x00000001 1147 #define CSCONFIG_COL_BIT_10 0x00000002 1148 #define CSCONFIG_COL_BIT_11 0x00000003 1149 1150 /* 1151 * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 1152 */ 1153 #define TIMING_CFG0_RWT 0xC0000000 1154 #define TIMING_CFG0_RWT_SHIFT 30 1155 #define TIMING_CFG0_WRT 0x30000000 1156 #define TIMING_CFG0_WRT_SHIFT 28 1157 #define TIMING_CFG0_RRT 0x0C000000 1158 #define TIMING_CFG0_RRT_SHIFT 26 1159 #define TIMING_CFG0_WWT 0x03000000 1160 #define TIMING_CFG0_WWT_SHIFT 24 1161 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 1162 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 1163 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 1164 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 1165 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 1166 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 1167 #define TIMING_CFG0_MRS_CYC 0x0000000F 1168 #define TIMING_CFG0_MRS_CYC_SHIFT 0 1169 1170 /* 1171 * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 1172 */ 1173 #define TIMING_CFG1_PRETOACT 0x70000000 1174 #define TIMING_CFG1_PRETOACT_SHIFT 28 1175 #define TIMING_CFG1_ACTTOPRE 0x0F000000 1176 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 1177 #define TIMING_CFG1_ACTTORW 0x00700000 1178 #define TIMING_CFG1_ACTTORW_SHIFT 20 1179 #define TIMING_CFG1_CASLAT 0x00070000 1180 #define TIMING_CFG1_CASLAT_SHIFT 16 1181 #define TIMING_CFG1_REFREC 0x0000F000 1182 #define TIMING_CFG1_REFREC_SHIFT 12 1183 #define TIMING_CFG1_WRREC 0x00000700 1184 #define TIMING_CFG1_WRREC_SHIFT 8 1185 #define TIMING_CFG1_ACTTOACT 0x00000070 1186 #define TIMING_CFG1_ACTTOACT_SHIFT 4 1187 #define TIMING_CFG1_WRTORD 0x00000007 1188 #define TIMING_CFG1_WRTORD_SHIFT 0 1189 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 1190 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 1191 #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 1192 #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 1193 #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 1194 #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 1195 #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 1196 1197 /* 1198 * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 1199 */ 1200 #define TIMING_CFG2_CPO 0x0F800000 1201 #define TIMING_CFG2_CPO_SHIFT 23 1202 #define TIMING_CFG2_ACSM 0x00080000 1203 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 1204 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 1205 /* default (= CASLAT + 1) */ 1206 #define TIMING_CFG2_CPO_DEF 0x00000000 1207 1208 #define TIMING_CFG2_ADD_LAT 0x70000000 1209 #define TIMING_CFG2_ADD_LAT_SHIFT 28 1210 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 1211 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 1212 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 1213 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 1214 #define TIMING_CFG2_CKE_PLS 0x000001C0 1215 #define TIMING_CFG2_CKE_PLS_SHIFT 6 1216 #define TIMING_CFG2_FOUR_ACT 0x0000003F 1217 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 1218 1219 /* 1220 * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 1221 */ 1222 #define TIMING_CFG3_EXT_REFREC 0x00070000 1223 #define TIMING_CFG3_EXT_REFREC_SHIFT 16 1224 1225 /* 1226 * DDR_SDRAM_CFG - DDR SDRAM Control Configuration 1227 */ 1228 #define SDRAM_CFG_MEM_EN 0x80000000 1229 #define SDRAM_CFG_SREN 0x40000000 1230 #define SDRAM_CFG_ECC_EN 0x20000000 1231 #define SDRAM_CFG_RD_EN 0x10000000 1232 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 1233 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 1234 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 1235 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 1236 #define SDRAM_CFG_DYN_PWR 0x00200000 1237 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) 1238 #define SDRAM_CFG_DBW_MASK 0x00180000 1239 #define SDRAM_CFG_DBW_16 0x00100000 1240 #define SDRAM_CFG_DBW_32 0x00080000 1241 #else 1242 #define SDRAM_CFG_32_BE 0x00080000 1243 #endif 1244 #if !defined(CONFIG_ARCH_MPC8308) 1245 #define SDRAM_CFG_8_BE 0x00040000 1246 #endif 1247 #define SDRAM_CFG_NCAP 0x00020000 1248 #define SDRAM_CFG_2T_EN 0x00008000 1249 #define SDRAM_CFG_HSE 0x00000008 1250 #define SDRAM_CFG_BI 0x00000001 1251 1252 /* 1253 * DDR_SDRAM_MODE - DDR SDRAM Mode Register 1254 */ 1255 #define SDRAM_MODE_ESD 0xFFFF0000 1256 #define SDRAM_MODE_ESD_SHIFT 16 1257 #define SDRAM_MODE_SD 0x0000FFFF 1258 #define SDRAM_MODE_SD_SHIFT 0 1259 /* select extended mode reg */ 1260 #define DDR_MODE_EXT_MODEREG 0x4000 1261 /* operating mode, mask */ 1262 #define DDR_MODE_EXT_OPMODE 0x3FF8 1263 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 1264 /* QFC / compatibility, mask */ 1265 #define DDR_MODE_QFC 0x0004 1266 /* compatible to older SDRAMs */ 1267 #define DDR_MODE_QFC_COMP 0x0000 1268 /* weak drivers */ 1269 #define DDR_MODE_WEAK 0x0002 1270 /* disable DLL */ 1271 #define DDR_MODE_DLL_DIS 0x0001 1272 /* CAS latency, mask */ 1273 #define DDR_MODE_CASLAT 0x0070 1274 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 1275 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 1276 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 1277 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 1278 /* sequential burst */ 1279 #define DDR_MODE_BTYPE_SEQ 0x0000 1280 /* interleaved burst */ 1281 #define DDR_MODE_BTYPE_ILVD 0x0008 1282 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 1283 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 1284 /* exact value for 7.8125us */ 1285 #define DDR_REFINT_166MHZ_7US 1302 1286 /* use 256 cycles as a starting point */ 1287 #define DDR_BSTOPRE 256 1288 /* select mode register */ 1289 #define DDR_MODE_MODEREG 0x0000 1290 1291 /* 1292 * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 1293 */ 1294 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 1295 #define SDRAM_INTERVAL_REFINT_SHIFT 16 1296 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 1297 1298 /* 1299 * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 1300 */ 1301 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 1302 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 1303 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 1304 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 1305 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 1306 1307 /* 1308 * ECC_ERR_INJECT - Memory data path error injection mask ECC 1309 */ 1310 /* ECC Mirror Byte */ 1311 #define ECC_ERR_INJECT_EMB (0x80000000 >> 22) 1312 /* Error Injection Enable */ 1313 #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23) 1314 /* ECC Erroe Injection Enable */ 1315 #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24) 1316 #define ECC_ERR_INJECT_EEIM_SHIFT 0 1317 1318 /* 1319 * CAPTURE_ECC - Memory data path read capture ECC 1320 */ 1321 #define CAPTURE_ECC_ECE (0xff000000 >> 24) 1322 #define CAPTURE_ECC_ECE_SHIFT 0 1323 1324 /* 1325 * ERR_DETECT - Memory error detect 1326 */ 1327 /* Multiple Memory Errors */ 1328 #define ECC_ERROR_DETECT_MME (0x80000000 >> 0) 1329 /* Multiple-Bit Error */ 1330 #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28) 1331 /* Single-Bit ECC Error Pickup */ 1332 #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29) 1333 /* Memory Select Error */ 1334 #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31) 1335 1336 /* 1337 * ERR_DISABLE - Memory error disable 1338 */ 1339 /* Multiple-Bit ECC Error Disable */ 1340 #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28) 1341 /* Sinle-Bit ECC Error disable */ 1342 #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29) 1343 /* Memory Select Error Disable */ 1344 #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31) 1345 #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \ 1346 ECC_ERROR_DISABLE_SBED | \ 1347 ECC_ERROR_DISABLE_MBED)) 1348 1349 /* 1350 * ERR_INT_EN - Memory error interrupt enable 1351 */ 1352 /* Multiple-Bit ECC Error Interrupt Enable */ 1353 #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28) 1354 /* Single-Bit ECC Error Interrupt Enable */ 1355 #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29) 1356 /* Memory Select Error Interrupt Enable */ 1357 #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31) 1358 #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \ 1359 ECC_ERR_INT_EN_SBEE | \ 1360 ECC_ERR_INT_EN_MSEE)) 1361 1362 /* 1363 * CAPTURE_ATTRIBUTES - Memory error attributes capture 1364 */ 1365 /* Data Beat Num */ 1366 #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1) 1367 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 1368 /* Transaction Size */ 1369 #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6) 1370 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1371 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1372 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1373 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1374 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1375 /* Transaction Source */ 1376 #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11) 1377 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1378 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1379 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1380 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1381 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1382 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1383 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1384 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1385 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1386 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1387 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1388 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1389 /* Transaction Type */ 1390 #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18) 1391 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1392 #define ECC_CAPT_ATTR_TTYP_READ 0x2 1393 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1394 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1395 #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */ 1396 1397 /* 1398 * ERR_SBE - Single bit ECC memory error management 1399 */ 1400 /* Single-Bit Error Threshold 0..255 */ 1401 #define ECC_ERROR_MAN_SBET (0xff000000 >> 8) 1402 #define ECC_ERROR_MAN_SBET_SHIFT 16 1403 /* Single Bit Error Counter 0..255 */ 1404 #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) 1405 #define ECC_ERROR_MAN_SBEC_SHIFT 0 1406 1407 #endif /* !CONFIG_MPC83XX_SDRAM */ 1408 1409 /* 1410 * CONFIG_ADDRESS - PCI Config Address Register 1411 */ 1412 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1413 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1414 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1415 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1416 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1417 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1418 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1419 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1420 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1421 1422 /* 1423 * POTAR - PCI Outbound Translation Address Register 1424 */ 1425 #define POTAR_TA_MASK 0x000fffff 1426 1427 /* 1428 * POBAR - PCI Outbound Base Address Register 1429 */ 1430 #define POBAR_BA_MASK 0x000fffff 1431 1432 /* 1433 * POCMR - PCI Outbound Comparision Mask Register 1434 */ 1435 #define POCMR_EN 0x80000000 1436 /* 0-memory space 1-I/O space */ 1437 #define POCMR_IO 0x40000000 1438 #define POCMR_SE 0x20000000 /* streaming enable */ 1439 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1440 #define POCMR_CM_MASK 0x000fffff 1441 #define POCMR_CM_4G 0x00000000 1442 #define POCMR_CM_2G 0x00080000 1443 #define POCMR_CM_1G 0x000C0000 1444 #define POCMR_CM_512M 0x000E0000 1445 #define POCMR_CM_256M 0x000F0000 1446 #define POCMR_CM_128M 0x000F8000 1447 #define POCMR_CM_64M 0x000FC000 1448 #define POCMR_CM_32M 0x000FE000 1449 #define POCMR_CM_16M 0x000FF000 1450 #define POCMR_CM_8M 0x000FF800 1451 #define POCMR_CM_4M 0x000FFC00 1452 #define POCMR_CM_2M 0x000FFE00 1453 #define POCMR_CM_1M 0x000FFF00 1454 #define POCMR_CM_512K 0x000FFF80 1455 #define POCMR_CM_256K 0x000FFFC0 1456 #define POCMR_CM_128K 0x000FFFE0 1457 #define POCMR_CM_64K 0x000FFFF0 1458 #define POCMR_CM_32K 0x000FFFF8 1459 #define POCMR_CM_16K 0x000FFFFC 1460 #define POCMR_CM_8K 0x000FFFFE 1461 #define POCMR_CM_4K 0x000FFFFF 1462 1463 /* 1464 * PITAR - PCI Inbound Translation Address Register 1465 */ 1466 #define PITAR_TA_MASK 0x000fffff 1467 1468 /* 1469 * PIBAR - PCI Inbound Base/Extended Address Register 1470 */ 1471 #define PIBAR_MASK 0xffffffff 1472 #define PIEBAR_EBA_MASK 0x000fffff 1473 1474 /* 1475 * PIWAR - PCI Inbound Windows Attributes Register 1476 */ 1477 #define PIWAR_EN 0x80000000 1478 #define PIWAR_PF 0x20000000 1479 #define PIWAR_RTT_MASK 0x000f0000 1480 #define PIWAR_RTT_NO_SNOOP 0x00040000 1481 #define PIWAR_RTT_SNOOP 0x00050000 1482 #define PIWAR_WTT_MASK 0x0000f000 1483 #define PIWAR_WTT_NO_SNOOP 0x00004000 1484 #define PIWAR_WTT_SNOOP 0x00005000 1485 #define PIWAR_IWS_MASK 0x0000003F 1486 #define PIWAR_IWS_4K 0x0000000B 1487 #define PIWAR_IWS_8K 0x0000000C 1488 #define PIWAR_IWS_16K 0x0000000D 1489 #define PIWAR_IWS_32K 0x0000000E 1490 #define PIWAR_IWS_64K 0x0000000F 1491 #define PIWAR_IWS_128K 0x00000010 1492 #define PIWAR_IWS_256K 0x00000011 1493 #define PIWAR_IWS_512K 0x00000012 1494 #define PIWAR_IWS_1M 0x00000013 1495 #define PIWAR_IWS_2M 0x00000014 1496 #define PIWAR_IWS_4M 0x00000015 1497 #define PIWAR_IWS_8M 0x00000016 1498 #define PIWAR_IWS_16M 0x00000017 1499 #define PIWAR_IWS_32M 0x00000018 1500 #define PIWAR_IWS_64M 0x00000019 1501 #define PIWAR_IWS_128M 0x0000001A 1502 #define PIWAR_IWS_256M 0x0000001B 1503 #define PIWAR_IWS_512M 0x0000001C 1504 #define PIWAR_IWS_1G 0x0000001D 1505 #define PIWAR_IWS_2G 0x0000001E 1506 1507 /* 1508 * PMCCR1 - PCI Configuration Register 1 1509 */ 1510 #define PMCCR1_POWER_OFF 0x00000020 1511 1512 #ifndef CONFIG_RAM 1513 /* 1514 * DDRCDR - DDR Control Driver Register 1515 */ 1516 #define DDRCDR_DHC_EN 0x80000000 1517 #define DDRCDR_EN 0x40000000 1518 #define DDRCDR_PZ 0x3C000000 1519 #define DDRCDR_PZ_MAXZ 0x00000000 1520 #define DDRCDR_PZ_HIZ 0x20000000 1521 #define DDRCDR_PZ_NOMZ 0x30000000 1522 #define DDRCDR_PZ_LOZ 0x38000000 1523 #define DDRCDR_PZ_MINZ 0x3C000000 1524 #define DDRCDR_NZ 0x3C000000 1525 #define DDRCDR_NZ_MAXZ 0x00000000 1526 #define DDRCDR_NZ_HIZ 0x02000000 1527 #define DDRCDR_NZ_NOMZ 0x03000000 1528 #define DDRCDR_NZ_LOZ 0x03800000 1529 #define DDRCDR_NZ_MINZ 0x03C00000 1530 #define DDRCDR_ODT 0x00080000 1531 #define DDRCDR_DDR_CFG 0x00040000 1532 #define DDRCDR_M_ODR 0x00000002 1533 #define DDRCDR_Q_DRN 0x00000001 1534 #endif /* !CONFIG_RAM */ 1535 1536 /* 1537 * PCIE Bridge Register 1538 */ 1539 #define PEX_CSB_CTRL_OBPIOE 0x00000001 1540 #define PEX_CSB_CTRL_IBPIOE 0x00000002 1541 #define PEX_CSB_CTRL_WDMAE 0x00000004 1542 #define PEX_CSB_CTRL_RDMAE 0x00000008 1543 1544 #define PEX_CSB_OBCTRL_PIOE 0x00000001 1545 #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1546 #define PEX_CSB_OBCTRL_IOWE 0x00000004 1547 #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1548 1549 #define PEX_CSB_IBCTRL_PIOE 0x00000001 1550 1551 #define PEX_OWAR_EN 0x00000001 1552 #define PEX_OWAR_TYPE_CFG 0x00000000 1553 #define PEX_OWAR_TYPE_IO 0x00000002 1554 #define PEX_OWAR_TYPE_MEM 0x00000004 1555 #define PEX_OWAR_RLXO 0x00000008 1556 #define PEX_OWAR_NANP 0x00000010 1557 #define PEX_OWAR_SIZE 0xFFFFF000 1558 1559 #define PEX_IWAR_EN 0x00000001 1560 #define PEX_IWAR_TYPE_INT 0x00000000 1561 #define PEX_IWAR_TYPE_PF 0x00000004 1562 #define PEX_IWAR_TYPE_NO_PF 0x00000006 1563 #define PEX_IWAR_NSOV 0x00000008 1564 #define PEX_IWAR_NSNP 0x00000010 1565 #define PEX_IWAR_SIZE 0xFFFFF000 1566 #define PEX_IWAR_SIZE_1M 0x000FF000 1567 #define PEX_IWAR_SIZE_2M 0x001FF000 1568 #define PEX_IWAR_SIZE_4M 0x003FF000 1569 #define PEX_IWAR_SIZE_8M 0x007FF000 1570 #define PEX_IWAR_SIZE_16M 0x00FFF000 1571 #define PEX_IWAR_SIZE_32M 0x01FFF000 1572 #define PEX_IWAR_SIZE_64M 0x03FFF000 1573 #define PEX_IWAR_SIZE_128M 0x07FFF000 1574 #define PEX_IWAR_SIZE_256M 0x0FFFF000 1575 1576 #define PEX_GCLK_RATIO 0x440 1577 1578 #ifndef __ASSEMBLY__ 1579 struct pci_region; 1580 void mpc83xx_pci_init(int num_buses, struct pci_region **reg); 1581 void mpc83xx_pcislave_unlock(int bus); 1582 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); 1583 #endif 1584 1585 #endif /* __MPC83XX_H__ */ 1586