Searched refs:APLL_MODE_SHIFT (Results 1 – 14 of 14) sorted by relevance
| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | cru_rk3036.h | 94 APLL_MODE_SHIFT = 0, enumerator
95 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
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| A D | cru_rk3128.h | 107 APLL_MODE_SHIFT = 0, enumerator
108 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
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| A D | cru_rk322x.h | 101 APLL_MODE_SHIFT = 0, enumerator
102 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
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| A D | cru_rk3288.h | 203 APLL_MODE_SHIFT = 0, enumerator
204 APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT,
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| A D | cru_rk3188.h | 169 APLL_MODE_SHIFT = 0, enumerator
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| A D | cru_px30.h | 157 APLL_MODE_SHIFT = 0, enumerator
158 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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| /u-boot/arch/arm/include/asm/arch-rk3308/ |
| A D | cru_rk3308.h | 134 APLL_MODE_SHIFT = 0, enumerator
135 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3188.c | 203 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
204 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_configure_cpu()
223 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
224 APLL_MODE_NORMAL << APLL_MODE_SHIFT); in rkclk_configure_cpu()
238 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
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| A D | clk_rk3036.c | 93 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_init()
170 APLL_MODE_NORM << APLL_MODE_SHIFT); in rkclk_init()
182 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
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| A D | clk_rk322x.c | 95 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_init()
172 APLL_MODE_NORM << APLL_MODE_SHIFT); in rkclk_init()
184 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
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| A D | clk_rk3128.c | 154 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_init()
231 APLL_MODE_NORM << APLL_MODE_SHIFT | in rkclk_init()
250 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
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| A D | clk_rk3288.c | 506 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rk3288_clk_configure_cpu()
540 APLL_MODE_NORMAL << APLL_MODE_SHIFT); in rk3288_clk_configure_cpu()
552 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
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| A D | clk_rk3328.c | 76 APLL_MODE_SHIFT = 0, enumerator
222 mode_shift = APLL_MODE_SHIFT; in rkclk_set_pll()
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| A D | clk_px30.c | 84 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
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Completed in 23 milliseconds