Searched refs:AR71XX_DDR_REG_TAP_CTRL0 (Results 1 – 5 of 5) sorted by relevance
| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | ddr.c | 181 writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
225 writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
267 tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
275 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
330 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
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| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | ddr.c | 298 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
404 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
419 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
426 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
469 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
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| /u-boot/arch/mips/mach-ath79/ar934x/ |
| A D | ddr.c | 138 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); in ar934x_ddr_init()
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| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | ddr.c | 301 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); in qca956x_ddr_init()
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| /u-boot/arch/mips/mach-ath79/include/mach/ |
| A D | ar71xx_regs.h | 221 #define AR71XX_DDR_REG_TAP_CTRL0 0x1c macro
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