Searched refs:AR71XX_DDR_REG_TAP_CTRL1 (Results 1 – 5 of 5) sorted by relevance
| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | ddr.c | 301 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
407 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
427 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
470 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /u-boot/arch/mips/mach-ath79/ar934x/ |
| A D | ddr.c | 139 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); in ar934x_ddr_init()
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| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | ddr.c | 302 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); in qca956x_ddr_init()
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| /u-boot/arch/mips/mach-ath79/include/mach/ |
| A D | ar71xx_regs.h | 222 #define AR71XX_DDR_REG_TAP_CTRL1 0x20 macro
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