Searched refs:AR71XX_PLL_BASE (Results 1 – 8 of 8) sorted by relevance
| /u-boot/arch/mips/mach-ath79/ |
| A D | reset.c | 118 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar933x()
153 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar934x()
204 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in qca956x_sgmii_cal()
400 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_qca956x()
481 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in usb_reset_qca953x()
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| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | clk.c | 38 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
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| A D | lowlevel_init.S | 157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
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| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | clk.c | 38 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
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| A D | lowlevel_init.S | 134 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
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| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | clk.c | 188 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in set_val()
224 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in qca956x_pll_init()
327 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in get_clocks()
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| /u-boot/arch/mips/mach-ath79/ar934x/ |
| A D | clk.c | 113 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init()
271 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in ar934x_update_clock()
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| /u-boot/arch/mips/mach-ath79/include/mach/ |
| A D | ar71xx_regs.h | 46 #define AR71XX_PLL_BASE \ macro
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