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Searched refs:AR934X_SRIF_DDR_DPLL2_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/ar934x/
A Dclk.c122 writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_pll_init()
/u-boot/arch/mips/mach-ath79/include/mach/
A Dar71xx_regs.h1170 #define AR934X_SRIF_DDR_DPLL2_REG 0x244 macro

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