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Searched refs:BASE_CFG (Results 1 – 16 of 16) sorted by relevance

/u-boot/arch/mips/mach-mscc/
A Dreset.c16 register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); in _machine_restart()
22 writel(reg, BASE_CFG + ICPU_GENERAL_CTRL); in _machine_restart()
24 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); in _machine_restart()
26 writel(readl(BASE_CFG + ICPU_RESET) | in _machine_restart()
29 BASE_CFG + ICPU_RESET); in _machine_restart()
34 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in _machine_restart()
43 writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) | in _machine_restart()
45 BASE_CFG + ICPU_MEMCTRL_CTRL); in _machine_restart()
47 while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & in _machine_restart()
52 writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET); in _machine_restart()
[all …]
A Dcpu.c88 ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG); in mach_cpu_init()
92 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); in mach_cpu_init()
96 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); in mach_cpu_init()
101 ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG); in mach_cpu_init()
107 writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); in mach_cpu_init()
108 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); in mach_cpu_init()
109 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); in mach_cpu_init()
110 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); in mach_cpu_init()
A Ddram.c38 if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) in vcoreiii_ddr_init()
53 clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in vcoreiii_ddr_init()
56 readl(BASE_CFG + ICPU_GENERAL_CTRL); in vcoreiii_ddr_init()
/u-boot/arch/mips/mach-mscc/include/mach/
A Dddr.h398 BASE_CFG + ICPU_TIMER_CTRL(0)); in sleep_100ns()
416 writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6)); in hal_vcoreiii_ddr_failed()
443 writel(0, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_failed()
473 writel(readl(BASE_CFG + ICPU_RESET) | in hal_vcoreiii_ddr_reset_assert()
496 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), BASE_CFG + ICPU_MEMCTRL_STAT); in hal_vcoreiii_ddr_verified()
511 BASE_CFG + ICPU_MEMCTRL_STAT); in look_for()
551 BASE_CFG + ICPU_MEMCTRL_STAT); in look_past()
665 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
667 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
669 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
[all …]
/u-boot/board/mscc/common/
A Dspi.c22 BASE_CFG + ICPU_SW_MODE); in external_cs_manage()
23 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in external_cs_manage()
27 writel(0, BASE_CFG + ICPU_SW_MODE); in external_cs_manage()
28 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in external_cs_manage()
/u-boot/board/mscc/ocelot/
A Docelot.c34 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in mscc_switch_reset()
74 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
75 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in board_early_init_r()
/u-boot/arch/mips/mach-mscc/include/mach/luton/
A Dluton.h18 #define BASE_CFG ((void __iomem *)0x70000000) macro
/u-boot/arch/mips/mach-mscc/include/mach/servalt/
A Dservalt.h18 #define BASE_CFG ((void __iomem *)0x70000000) macro
/u-boot/arch/mips/mach-mscc/include/mach/jr2/
A Djr2.h18 #define BASE_CFG ((void __iomem *)0x70000000) macro
/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
A Docelot.h18 #define BASE_CFG ((void __iomem *)0x70000000) macro
/u-boot/arch/mips/mach-mscc/include/mach/serval/
A Dserval.h18 #define BASE_CFG ((void __iomem *)0x70000000) macro
/u-boot/board/mscc/servalt/
A Dservalt.c22 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/u-boot/board/mscc/jr2/
A Djr2.c25 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
26 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in board_early_init_r()
/u-boot/board/mscc/luton/
A Dluton.c29 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/u-boot/board/mscc/serval/
A Dserval.c22 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/u-boot/drivers/net/mscc_eswitch/
A Dserval_switch.c415 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in serval_stop()

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