Searched refs:BASE_DEVCPU_GCB (Results 1 – 15 of 15) sorted by relevance
| /u-boot/arch/mips/mach-mscc/ |
| A D | gpio.c | 15 val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0)); in mscc_gpio_set_alternate()
16 val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1)); in mscc_gpio_set_alternate()
32 writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0)); in mscc_gpio_set_alternate()
33 writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1)); in mscc_gpio_set_alternate()
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| A D | reset.c | 37 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
55 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
65 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); in _machine_restart()
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| A D | phy.c | 31 writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev)); in mscc_phy_rd_wr()
40 data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev)); in mscc_phy_rd_wr()
45 data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev)); in mscc_phy_rd_wr()
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| /u-boot/board/mscc/ocelot/ |
| A D | ocelot.c | 35 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in mscc_switch_reset()
37 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, in mscc_switch_reset()
45 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in mscc_switch_reset()
46 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); in mscc_switch_reset()
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| /u-boot/board/mscc/jr2/ |
| A D | jr2.c | 48 reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0); in vcoreiii_gpio_set_alternate()
49 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1); in vcoreiii_gpio_set_alternate()
53 reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0); in vcoreiii_gpio_set_alternate()
54 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1); in vcoreiii_gpio_set_alternate()
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| /u-boot/arch/mips/mach-mscc/include/mach/luton/ |
| A D | luton.h | 19 #define BASE_DEVCPU_GCB ((void __iomem *)0x60070000) macro
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| /u-boot/arch/mips/mach-mscc/include/mach/servalt/ |
| A D | servalt.h | 19 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000) macro
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| /u-boot/arch/mips/mach-mscc/include/mach/jr2/ |
| A D | jr2.h | 19 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000) macro
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| /u-boot/arch/mips/mach-mscc/include/mach/ocelot/ |
| A D | ocelot.h | 19 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000) macro
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| /u-boot/arch/mips/mach-mscc/include/mach/serval/ |
| A D | serval.h | 19 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000) macro
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| /u-boot/board/mscc/luton/ |
| A D | luton.c | 53 u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF; in do_board_detect()
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| /u-boot/arch/mips/mach-mscc/include/mach/ |
| A D | ddr.h | 418 clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in hal_vcoreiii_ddr_failed()
452 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in hal_vcoreiii_ddr_reset_assert()
453 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); in hal_vcoreiii_ddr_reset_assert()
460 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); in hal_vcoreiii_ddr_reset_release()
461 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); in hal_vcoreiii_ddr_reset_release()
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| /u-boot/drivers/net/mscc_eswitch/ |
| A D | servalt_switch.c | 141 writel(0, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG); in mscc_phy_reset()
143 | PHY_CFG_ENA, BASE_DEVCPU_GCB + GCB_PHY_CFG + PHY_CFG); in mscc_phy_reset()
144 if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + GCB_PHY_CFG) + in mscc_phy_reset()
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| A D | ocelot_switch.c | 185 writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG); in mscc_phy_reset()
187 | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG); in mscc_phy_reset()
188 if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) + in mscc_phy_reset()
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| A D | serval_switch.c | 416 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); in serval_stop()
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