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Searched refs:BIT_ULL (Results 1 – 15 of 15) sorted by relevance

/u-boot/drivers/net/octeontx/
A Dbgx.h44 #define CMR_PKT_TX_EN BIT_ULL(13)
45 #define CMR_PKT_RX_EN BIT_ULL(14)
46 #define CMR_EN BIT_ULL(15)
64 #define RX_DMACX_CAM_EN BIT_ULL(48)
93 #define SPU_CTL_LOW_POWER BIT_ULL(11)
95 #define SPU_CTL_RESET BIT_ULL(15)
114 #define SPU_AN_CTL_AN_EN BIT_ULL(12)
140 #define SMU_TX_CTL_DIC_EN BIT_ULL(0)
141 #define SMU_TX_CTL_UNI_EN BIT_ULL(1)
145 #define SMU_CTL_RX_IDLE BIT_ULL(0)
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A Dnicvf_queues.h55 #define SND_QUEUE_LEN BIT_ULL((SND_QSIZE + 10))
61 #define CMP_QUEUE_LEN BIT_ULL((CMP_QSIZE + 10))
66 #define RCV_BUF_COUNT BIT_ULL((RBDR_SIZE + 13))
81 #define NICVF_RCV_BUF_ALIGN_BYTES BIT_ULL(NICVF_RCV_BUF_ALIGN)
88 #define NICVF_SQ_EN BIT_ULL(19)
91 #define NICVF_CQ_RESET BIT_ULL(41)
92 #define NICVF_SQ_RESET BIT_ULL(17)
93 #define NICVF_RBDR_RESET BIT_ULL(43)
/u-boot/arch/x86/include/asm/
A Dmsr-index.h118 #define MISC_ENABLE_FAST_STRING BIT_ULL(0)
119 #define MISC_ENABLE_TCC BIT_ULL(1)
120 #define MISC_DISABLE_TURBO BIT_ULL(6)
121 #define MISC_ENABLE_EMON BIT_ULL(7)
122 #define MISC_ENABLE_BTS_UNAVAIL BIT_ULL(11)
125 #define MISC_ENABLE_MWAIT BIT_ULL(18)
128 #define MISC_ENABLE_XD_DISABLE BIT_ULL(34)
131 #define MISC_ENABLE_X87_COMPAT BIT_ULL(2)
132 #define MISC_ENABLE_TM1 BIT_ULL(3)
137 #define MISC_ENABLE_FERR BIT_ULL(10)
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/u-boot/drivers/usb/host/
A Ddwc3-octeon-glue.c34 #define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
37 #define UCTL_CTL_UCTL_RST BIT_ULL(0)
38 #define UCTL_CTL_UAHC_RST BIT_ULL(1)
39 #define UCTL_CTL_UPHY_RST BIT_ULL(2)
40 #define UCTL_CTL_DRD_MODE BIT_ULL(3)
41 #define UCTL_CTL_SCLK_EN BIT_ULL(4)
42 #define UCTL_CTL_HS_POWER_EN BIT_ULL(12)
43 #define UCTL_CTL_SS_POWER_EN BIT_ULL(14)
46 #define UCTL_CTL_H_CLK_EN BIT_ULL(30)
49 #define UCTL_CTL_REF_SSP_EN BIT_ULL(39)
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/u-boot/arch/mips/mach-octeon/include/mach/
A Dcvmx-regs.h40 #define MIO_BOOT_LOC_CFG_EN BIT_ULL(31)
48 #define MIO_FUS_DAT2_NOCRYPTO BIT_ULL(26)
49 #define MIO_FUS_DAT2_NOMUL BIT_ULL(27)
50 #define MIO_FUS_DAT2_DORM_CRYPTO BIT_ULL(34)
54 #define MIO_FUS_RCMD_PEND BIT_ULL(12)
58 #define RNM_CTL_STATUS_EER_VAL BIT_ULL(9)
/u-boot/drivers/spi/
A Docteon_spi.c36 #define MPI_CFG_ENABLE BIT_ULL(0)
37 #define MPI_CFG_IDLELO BIT_ULL(1)
38 #define MPI_CFG_CLK_CONT BIT_ULL(2)
39 #define MPI_CFG_WIREOR BIT_ULL(3)
40 #define MPI_CFG_LSBFIRST BIT_ULL(4)
42 #define MPI_CFG_CSHI BIT_ULL(7)
44 #define MPI_CFG_TRITX BIT_ULL(10)
45 #define MPI_CFG_CSLATE BIT_ULL(11)
46 #define MPI_CFG_CSENA0 BIT_ULL(12)
47 #define MPI_CFG_CSENA1 BIT_ULL(13)
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/u-boot/drivers/gpio/
A Docteon_gpio.c23 #define GPIO_BIT(x) BIT_ULL((x) & 0x3f)
37 #define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
38 #define GPIO_BIT_CFG_PIN_XOR BIT_ULL(1)
39 #define GPIO_BIT_CFG_INT_EN BIT_ULL(2)
/u-boot/drivers/i2c/
A Docteon_i2c.c26 #define TWSI_SW_SOVR BIT_ULL(55)
27 #define TWSI_SW_R BIT_ULL(56)
30 #define TWSI_SW_SLONLY BIT_ULL(62)
31 #define TWSI_SW_V BIT_ULL(63)
33 #define TWSI_INT_SDA_OVR BIT_ULL(8)
34 #define TWSI_INT_SCL_OVR BIT_ULL(9)
35 #define TWSI_INT_SDA BIT_ULL(10)
36 #define TWSI_INT_SCL BIT_ULL(11)
/u-boot/drivers/net/octeontx2/
A Dcgx_intf.c323 args->mode = BIT_ULL(CGX_MODE_10G_C2C_BIT); in mode_to_args()
327 args->mode = BIT_ULL(CGX_MODE_10G_C2M_BIT); in mode_to_args()
331 args->mode = BIT_ULL(CGX_MODE_10G_KR_BIT); in mode_to_args()
336 args->mode = BIT_ULL(CGX_MODE_25G_C2C_BIT); in mode_to_args()
340 args->mode = BIT_ULL(CGX_MODE_25G_2_C2C_BIT); in mode_to_args()
344 args->mode = BIT_ULL(CGX_MODE_50G_C2C_BIT); in mode_to_args()
348 args->mode = BIT_ULL(CGX_MODE_50G_4_C2C_BIT); in mode_to_args()
/u-boot/drivers/mtd/nand/raw/
A Docteontx_nand.c231 #define NDF_MISC_MB_DIS BIT_ULL(27)
239 #define NDF_MISC_RD_DONE BIT_ULL(6)
241 #define NDF_MISC_RD_VAL BIT_ULL(5)
243 #define NDF_MISC_RD_CMD BIT_ULL(4)
245 #define NDF_MISC_BT_DIS BIT_ULL(2)
247 #define NDF_MISC_EX_DIS BIT_ULL(1)
249 #define NDF_MISC_RST_FF BIT_ULL(0)
252 #define NDF_DMA_CFG_EN BIT_ULL(63)
254 #define NDF_DMA_CFG_RW BIT_ULL(62)
256 #define NDF_DMA_CFG_CLR BIT_ULL(61)
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/u-boot/include/
A Dvirtio.h439 return uc_priv->features & BIT_ULL(fbit); in __virtio_test_bit()
460 uc_priv->features |= BIT_ULL(fbit); in __virtio_set_bit()
481 uc_priv->features &= ~BIT_ULL(fbit); in __virtio_clear_bit()
/u-boot/include/linux/
A Dbitops.h12 #define BIT_ULL(nr) (1ULL << (nr)) macro
/u-boot/arch/arm/include/asm/
A Dgic-v3.h113 #define GICR_PENDBASER_PTZ BIT_ULL(62)
/u-boot/drivers/ram/octeon/
A Docteon3_lmc.c264 #define AREA_BASE_OFFSET BIT_ULL(26)
311 #define II_INC BIT_ULL(22) in test_dram_byte64()
312 #define II_MAX BIT_ULL(22) in test_dram_byte64()
313 #define K_INC BIT_ULL(14) in test_dram_byte64()
314 #define K_MAX BIT_ULL(kbitno) in test_dram_byte64()
315 #define J_INC BIT_ULL(9) in test_dram_byte64()
316 #define J_MAX BIT_ULL(12) in test_dram_byte64()
317 #define I_INC BIT_ULL(3) in test_dram_byte64()
318 #define I_MAX BIT_ULL(7) in test_dram_byte64()
/u-boot/arch/mips/include/asm/
A Dmipsregs.h714 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)

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