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Searched refs:CACHE_LINE_SIZE (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc86xx/
A Dcache.S10 #ifndef CACHE_LINE_SIZE
14 #if CACHE_LINE_SIZE == 128
16 #elif CACHE_LINE_SIZE == 32
18 #elif CACHE_LINE_SIZE == 16
20 #elif CACHE_LINE_SIZE == 8
57 lis r5,CACHE_LINE_SIZE
62 lis r5,CACHE_LINE_SIZE
75 li r5,CACHE_LINE_SIZE-1
84 addi r3,r3,CACHE_LINE_SIZE
89 addi r6,r6,CACHE_LINE_SIZE
[all …]
/u-boot/arch/nds32/lib/
A Dcache.c32 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) in CACHE_LINE_SIZE() function
47 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_all()
67 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_range()
142 line_size = CACHE_LINE_SIZE(DCACHE); in dcache_wbinval_all()
165 line_size = CACHE_LINE_SIZE(DCACHE); in flush_dcache_range()
180 line_size = CACHE_LINE_SIZE(DCACHE); in invalidate_dcache_range()
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_sdram.c574 flush_l1_v7(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
578 flush_l1_v6(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
A Dddr3_hw_training.h89 #define CACHE_LINE_SIZE 0x20 macro
/u-boot/arch/x86/
A DKconfig936 # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS

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