Searched refs:CHSCCDR_CLK_SEL_LDB_DI0 (Results 1 – 17 of 17) sorted by relevance
269 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()271 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
216 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_b850v3()262 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_bx50v3()
167 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
410 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display_clock()
437 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()439 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
462 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()464 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
341 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
179 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in enable_lvds()
288 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
660 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()662 CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
411 (CHSCCDR_CLK_SEL_LDB_DI0 << in setup_display()
486 (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
527 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
620 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
734 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
510 #define CHSCCDR_CLK_SEL_LDB_DI0 3 macro
485 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 in setup_display()
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