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Searched refs:CHX_ODT_CONFIG_DDR4_CA_ODT (Results 1 – 3 of 3) sorted by relevance

/u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/
A Dfsp-m.txt263 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
269 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
275 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
281 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
/u-boot/arch/x86/include/asm/arch-apollolake/fsp/
A Dfsp_m_upd.h266 #define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2 macro
/u-boot/arch/x86/dts/
A Dchromebook_coral.dts697 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
703 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
709 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
715 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;

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