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Searched refs:CLKMGR_ALTR_SDMMCCTR (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.c313 CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR); in clk_basic_init()
467 u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR, in clk_get_sdmmc_clk_hz()
471 clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) & in clk_get_sdmmc_clk_hz()
A Dclk-agilex.h129 #define CLKMGR_ALTR_SDMMCCTR 0xe4 macro

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