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Searched refs:CLKMGR_GEN5_MAINPLL_L4SRC (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c122 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); in cm_basic_init()
329 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); in cm_basic_init()
435 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC); in cm_get_l4_sp_clk_hz()
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_gen5.h68 #define CLKMGR_GEN5_MAINPLL_L4SRC 0x70 macro

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