CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK (reference) in projects: u-boot

Searched refs:CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A D	clock_manager_gen5.c	`239 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK); in cm_basic_init() 296 CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK), in cm_basic_init()`
/u-boot/arch/arm/mach-socfpga/include/mach/
A D	clock_manager_gen5.h	`86 #define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc macro`

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