CLKMGR_GEN5_SDRPLL_DDRDQSCLK (reference) in projects: u-boot

Searched refs:CLKMGR_GEN5_SDRPLL_DDRDQSCLK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A D	clock_manager_gen5.c	`236 socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK); in cm_basic_init() 288 CLKMGR_GEN5_SDRPLL_DDRDQSCLK), in cm_basic_init() 422 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK); in cm_get_sdram_clk_hz()`
/u-boot/arch/arm/mach-socfpga/include/mach/
A D	clock_manager_gen5.h	`85 #define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8 macro`

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