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Searched refs:CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_gen5.h204 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 macro
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c121 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, in cm_basic_init()

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