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Searched refs:CLKMGR_MAINPLL_MPUCLK (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.c277 CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK); in clk_basic_init()
437 u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK, in clk_get_mpu_clk_hz()
441 clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) & in clk_get_mpu_clk_hz()
A Dclk-agilex.h83 #define CLKMGR_MAINPLL_MPUCLK 0x3c macro

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