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Searched refs:CLKMGR_MAINPLL_NOCDIV (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.c279 CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV); in clk_basic_init()
458 clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> in clk_get_l4_main_clk_hz()
481 clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> in clk_get_l4_sp_clk_hz()
492 clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> in clk_get_l4_mp_clk_hz()
A Dclk-agilex.h85 #define CLKMGR_MAINPLL_NOCDIV 0x44 macro

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