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Searched refs:CLKMGR_MAINPLL_PLLC3 (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.c275 CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3); in clk_basic_init()
468 CLKMGR_MAINPLL_PLLC3, in clk_get_sdmmc_clk_hz()
553 clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) & in clk_get_emac_clk_hz()
A Dclk-agilex.h94 #define CLKMGR_MAINPLL_PLLC3 0x68 macro

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