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Searched refs:CLKMGR_PERPLL_PLLC0 (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.h113 #define CLKMGR_PERPLL_PLLC0 0xac macro
A Dclk-agilex.c287 CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0); in clk_basic_init()
439 CLKMGR_PERPLL_PLLC0); in clk_get_mpu_clk_hz()

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