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Searched refs:CLKMGR_PERPLL_PLLC2 (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-agilex.h116 #define CLKMGR_PERPLL_PLLC2 0xb8 macro
A Dclk-agilex.c289 CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2); in clk_basic_init()
561 clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) & in clk_get_emac_clk_hz()

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