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Searched refs:CLKMGR_PLLGLOB_REFCLKDIV_OFFSET (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c56 refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_basic_init()
83 refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_basic_init()
219 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_main_vco_clk_hz()
250 refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_get_per_vco_clk_hz()
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_s10.h132 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 macro
/u-boot/drivers/clk/altera/
A Dclk-agilex.h181 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 macro
A Dclk-agilex.c212 CLKMGR_PLLGLOB_REFCLKDIV_OFFSET; in calc_vocalib_pll()

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