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Searched refs:CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dwrap_pll_config.c111 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_gen5.h298 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 macro

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