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Searched refs:CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-socfpga/
A Dwrap_pll_config.c105 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
A Dclock_manager_gen5.c424 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; in cm_get_sdram_clk_hz()
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_gen5.h286 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 macro

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