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Searched refs:CLK_APMIXED_APLL1 (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c50 PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
111 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
112 FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
113 FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
114 FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
115 FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
116 FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
A Dclk-mt8183.c65 PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001,
148 FACTOR(CLK_TOP_APLL1_CK, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
149 FACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED),
150 FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED),
151 FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED),
A Dclk-mt8516.c46 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
99 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
A Dclk-mt8518.c46 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
100 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h190 #define CLK_APMIXED_APLL1 4 macro
A Dmt8516-clk.h18 #define CLK_APMIXED_APLL1 4 macro
A Dmt8518-clk.h15 #define CLK_APMIXED_APLL1 4 macro
A Dmt8183-clk.h20 #define CLK_APMIXED_APLL1 9 macro

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