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Searched refs:CLK_APMIXED_APLL2 (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c52 PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
117 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
118 FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
119 FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
120 FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
121 FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
122 FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
A Dclk-mt8183.c67 PLL(CLK_APMIXED_APLL2, 0x02b4, 0x02c4, 0x00000001,
152 FACTOR(CLK_TOP_APLL2_CK, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
153 FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED),
154 FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),
155 FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED),
A Dclk-mt8516.c48 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
103 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
A Dclk-mt8518.c48 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
102 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h191 #define CLK_APMIXED_APLL2 5 macro
A Dmt8516-clk.h19 #define CLK_APMIXED_APLL2 5 macro
A Dmt8518-clk.h16 #define CLK_APMIXED_APLL2 5 macro
A Dmt8183-clk.h21 #define CLK_APMIXED_APLL2 10 macro

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