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Searched refs:CLK_APMIXED_SGMIPLL (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/mach-mediatek/mt7629/
A Dinit.c38 [CLK_APMIXED_SGMIPLL] = 650000000, in mtk_pll_early_init()
/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h164 #define CLK_APMIXED_SGMIPLL 5 macro
A Dmt7622-clk.h171 #define CLK_APMIXED_SGMIPLL 8 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c66 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
131 FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
132 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
A Dclk-mt7629.c60 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
133 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
/u-boot/arch/arm/dts/
A Dmt7629.dtsi302 <&apmixedsys CLK_APMIXED_SGMIPLL>,

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