Searched refs:CLK_APMIXED_TRGPLL (Results 1 – 5 of 5) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7622-clk.h | 170 #define CLK_APMIXED_TRGPLL 7 macro
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| A D | mt7623-clk.h | 184 #define CLK_APMIXED_TRGPLL 7 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 60 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
718 GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
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| A D | clk-mt7622.c | 64 PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
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| /u-boot/arch/arm/dts/ |
| A D | mt7623.dtsi | 440 <&apmixedsys CLK_APMIXED_TRGPLL>;
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