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Searched refs:CLK_APMIXED_UNIV2PLL (Results 1 – 7 of 7) sorted by relevance

/u-boot/arch/arm/mach-mediatek/mt7629/
A Dinit.c35 [CLK_APMIXED_UNIV2PLL] = 1200000000, in mtk_pll_early_init()
/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h161 #define CLK_APMIXED_UNIV2PLL 2 macro
A Dmt7622-clk.h165 #define CLK_APMIXED_UNIV2PLL 2 macro
A Dmt8183-clk.h15 #define CLK_APMIXED_UNIV2PLL 4 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c54 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
114 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
A Dclk-mt7629.c54 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
117 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
A Dclk-mt8183.c53 PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
190 FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2, CLK_PARENT_APMIXED),

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