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Searched refs:CLK_BUS_MMC0 (Results 1 – 25 of 25) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dsun8i-v3s-ccu.h53 #define CLK_BUS_MMC0 22 macro
A Dsun8i-a23-a33-ccu.h51 #define CLK_BUS_MMC0 26 macro
A Dsun8i-a83t-ccu.h56 #define CLK_BUS_MMC0 22 macro
A Dsun50i-a64-ccu.h53 #define CLK_BUS_MMC0 31 macro
A Dsun8i-h3-ccu.h54 #define CLK_BUS_MMC0 22 macro
A Dsun50i-h616-ccu.h49 #define CLK_BUS_MMC0 63 macro
A Dsun50i-h6-ccu.h53 #define CLK_BUS_MMC0 67 macro
A Dsun8i-r40-ccu.h51 #define CLK_BUS_MMC0 32 macro
/u-boot/drivers/clk/sunxi/
A Dclk_v3s.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
A Dclk_a23.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
A Dclk_a64.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
A Dclk_a83t.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
A Dclk_h6.c17 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
A Dclk_h3.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
A Dclk_h616.c16 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
A Dclk_r40.c17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
/u-boot/arch/arm/dts/
A Dsun50i-h5.dtsi190 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
A Dsun8i-h3.dtsi244 clocks = <&ccu CLK_BUS_MMC0>,
A Dsun8i-v3s.dtsi204 clocks = <&ccu CLK_BUS_MMC0>,
A Dsun50i-h616.dtsi241 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
A Dsun8i-a23-a33.dtsi139 clocks = <&ccu CLK_BUS_MMC0>,
A Dsun8i-r40.dtsi187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
A Dsun50i-h6.dtsi432 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
A Dsun8i-a83t.dtsi492 clocks = <&ccu CLK_BUS_MMC0>,
A Dsun50i-a64.dtsi483 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;

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