Home
last modified time | relevance | path

Searched refs:CLK_BUS_OTG (Results 1 – 24 of 24) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dsun8i-v3s-ccu.h60 #define CLK_BUS_OTG 29 macro
A Dsun8i-a23-a33-ccu.h59 #define CLK_BUS_OTG 34 macro
A Dsun8i-a83t-ccu.h65 #define CLK_BUS_OTG 31 macro
A Dsun50i-a64-ccu.h63 #define CLK_BUS_OTG 41 macro
A Dsun8i-h3-ccu.h64 #define CLK_BUS_OTG 32 macro
A Dsun50i-h616-ccu.h98 #define CLK_BUS_OTG 112 macro
A Dsun9i-a80-ccu.h123 #define CLK_BUS_OTG 95 macro
A Dsun50i-h6-ccu.h102 #define CLK_BUS_OTG 116 macro
A Dsun8i-r40-ccu.h65 #define CLK_BUS_OTG 46 macro
/u-boot/drivers/clk/sunxi/
A Dclk_v3s.c21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
A Dclk_a23.c22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
A Dclk_a64.c23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
A Dclk_a83t.c23 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
A Dclk_h6.c47 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
A Dclk_h3.c23 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
A Dclk_h616.c56 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
A Dclk_r40.c25 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
/u-boot/arch/arm/dts/
A Dsun8i-v3s.dtsi276 clocks = <&ccu CLK_BUS_OTG>;
A Dsun50i-h616.dtsi501 clocks = <&ccu CLK_BUS_OTG>;
A Dsun8i-a23-a33.dtsi211 clocks = <&ccu CLK_BUS_OTG>;
A Dsun50i-h6.dtsi644 clocks = <&ccu CLK_BUS_OTG>;
A Dsun8i-a83t.dtsi558 clocks = <&ccu CLK_BUS_OTG>;
A Dsunxi-h3-h5.dtsi245 clocks = <&ccu CLK_BUS_OTG>;
A Dsun50i-a64.dtsi555 clocks = <&ccu CLK_BUS_OTG>;

Completed in 29 milliseconds