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Searched refs:CLK_BUS_UART2 (Results 1 – 25 of 26) sorted by relevance

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/u-boot/include/dt-bindings/clock/
A Dsun8i-v3s-ccu.h73 #define CLK_BUS_UART2 42 macro
A Dsun8i-a23-a33-ccu.h81 #define CLK_BUS_UART2 56 macro
A Dsun8i-a83t-ccu.h92 #define CLK_BUS_UART2 55 macro
A Dsun50i-a64-ccu.h91 #define CLK_BUS_UART2 69 macro
A Dsun8i-h3-ccu.h96 #define CLK_BUS_UART2 64 macro
A Dsun50i-h616-ccu.h54 #define CLK_BUS_UART2 68 macro
A Dsun9i-a80-ccu.h157 #define CLK_BUS_UART2 126 macro
A Dsun50i-h6-ccu.h58 #define CLK_BUS_UART2 72 macro
A Dsun8i-r40-ccu.h117 #define CLK_BUS_UART2 98 macro
/u-boot/drivers/clk/sunxi/
A Dclk_v3s.c25 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
A Dclk_a23.c28 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
A Dclk_a64.c31 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
A Dclk_a80.c30 [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
A Dclk_a83t.c30 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
A Dclk_h6.c22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
A Dclk_h3.c35 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
A Dclk_h616.c22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
A Dclk_r40.c37 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
/u-boot/arch/arm/dts/
A Dsun8i-v3s.dtsi439 clocks = <&ccu CLK_BUS_UART2>;
A Dsun50i-h616.dtsi328 clocks = <&ccu CLK_BUS_UART2>;
A Dsun8i-a23-a33.dtsi441 clocks = <&ccu CLK_BUS_UART2>;
A Dsun8i-r40.dtsi442 clocks = <&ccu CLK_BUS_UART2>;
A Dsun50i-h6.dtsi504 clocks = <&ccu CLK_BUS_UART2>;
A Dsunxi-h3-h5.dtsi699 clocks = <&ccu CLK_BUS_UART2>;
A Dsun50i-a64.dtsi911 clocks = <&ccu CLK_BUS_UART2>;

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