CLK_DIV_CDREX1_VAL (reference) in projects: u-boot

Searched refs:CLK_DIV_CDREX1_VAL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A D	exynos5_setup.h	`507 #define CLK_DIV_CDREX1_VAL NOT_AVAILABLE macro 775 #define CLK_DIV_CDREX1_VAL 0x300 macro`
A D	clock_init_exynos5.c	`912 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1); in exynos5420_system_clock_init()`

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