Searched refs:CLK_DIV_CORE0_VAL (Results 1 – 2 of 2) sorted by relevance
| /u-boot/arch/arm/mach-exynos/ | ||
| A D | exynos5_setup.h | 133 #define CLK_DIV_CORE0_VAL 0x00120000 macro |
| A D | clock_init_exynos5.c | 670 writel(CLK_DIV_CORE0_VAL, &clk->div_core0); in exynos5250_system_clock_init() |
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