CLK_DIV_FSYS1_VAL (reference) in projects: u-boot

Searched refs:CLK_DIV_FSYS1_VAL (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A D	clock_init_exynos4.c	`69 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()`
A D	exynos5_setup.h	`489 #define CLK_DIV_FSYS1_VAL NOT_AVAILABLE macro 757 #define CLK_DIV_FSYS1_VAL 0x04f13c4f macro`
A D	exynos4_setup.h	`204 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro`
A D	clock_init_exynos5.c	`942 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()`
/u-boot/board/samsung/trats/
A D	trats.c	`332 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); in board_clock_init()`
A D	setup.h	`156 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ macro`

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