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Searched refs:CLK_DIV_PERIC4_VAL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Dexynos5_setup.h690 #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE macro
873 #define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \ macro
A Dclock_init_exynos5.c956 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4); in exynos5420_system_clock_init()

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