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Searched refs:CLK_HCLK_ARM_PLL_DIV_2 (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-lpc32xx/
A Dclk.c125 case CLK_HCLK_ARM_PLL_DIV_2: in get_sdram_clk_rate()
/u-boot/arch/arm/include/asm/arch-lpc32xx/
A Dclk.h81 #define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) macro

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