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Searched refs:CLK_PERI_PWM1_PD (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h135 #define CLK_PERI_PWM1_PD 1 macro
A Dmt7622-clk.h133 #define CLK_PERI_PWM1_PD 1 macro
/u-boot/arch/arm/dts/
A Dmt7629.dtsi345 <&pericfg CLK_PERI_PWM1_PD>;
A Dmt7622.dtsi415 <&pericfg CLK_PERI_PWM1_PD>,
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c425 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
A Dclk-mt7629.c473 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),

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