Searched refs:CLK_ROOT_ON (Results 1 – 8 of 8) sorted by relevance
| /u-boot/arch/arm/mach-imx/imx8m/ |
| A D | clock_imx8mm.c | 155 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
161 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_disable_bypass()
281 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
287 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
314 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
383 clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | in init_nand_clk()
438 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | in clock_init()
823 target = CLK_ROOT_ON | enet1_ref | in set_clk_eqos()
828 target = CLK_ROOT_ON | in set_clk_eqos()
913 target = CLK_ROOT_ON | enet1_ref | in set_clk_enet()
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| A D | clock_imx8mq.c | 385 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
387 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
389 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
401 CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) | in init_nand_clk()
412 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
472 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | in set_clk_qspi()
509 target = CLK_ROOT_ON | enet1_ref | in set_clk_enet()
514 target = CLK_ROOT_ON | in set_clk_enet()
565 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
571 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_disable_bypass()
[all …]
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| A D | clock_slice.c | 1743 return (val & CLK_ROOT_ON) ? 1 : 0; in clock_root_enabled()
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| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | clock.c | 89 target = CLK_ROOT_ON | in enable_usboh3_clk()
540 target = CLK_ROOT_ON | in enable_i2c_clk()
600 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
605 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
610 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
615 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
620 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_uart()
711 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK | in init_clk_wdog()
998 target = CLK_ROOT_ON | enet1_ref | in set_clk_enet()
1008 target = CLK_ROOT_ON | enet2_ref | in set_clk_enet()
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| A D | clock_slice.c | 715 val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT | in clock_root_cfg()
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| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddr_init.c | 113 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | in ddr_init()
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| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| A D | clock.h | 210 #define CLK_ROOT_ON BIT(28) macro
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| /u-boot/arch/arm/include/asm/arch-mx7/ |
| A D | crm_regs.h | 2080 #define CLK_ROOT_ON 0x10000000 macro
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