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Searched refs:CLK_ROOT_POST_DIV (Results 1 – 5 of 5) sorted by relevance

/u-boot/arch/arm/mach-imx/mx7/
A Dclock.c92 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in enable_usboh3_clk()
567 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); in init_clk_esdhc()
572 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); in init_clk_esdhc()
577 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); in init_clk_esdhc()
602 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in init_clk_uart()
607 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in init_clk_uart()
612 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in init_clk_uart()
617 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in init_clk_uart()
622 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in init_clk_uart()
627 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in init_clk_uart()
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/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mm.c384 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */ in init_nand_clk()
820 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in set_clk_eqos()
825 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in set_clk_eqos()
831 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); in set_clk_eqos()
867 CLK_ROOT_POST_DIV(eqos_post_div - 1); in imx_eqos_txclk_set_rate()
910 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in set_clk_enet()
915 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in set_clk_enet()
921 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); in set_clk_enet()
A Dclock_imx8mq.c402 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); in init_nand_clk()
506 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in set_clk_enet()
511 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); in set_clk_enet()
517 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); in set_clk_enet()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock.h243 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) macro
/u-boot/arch/arm/include/asm/arch-mx7/
A Dcrm_regs.h2098 #define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) macro

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