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Searched refs:CLK_SPI1 (Results 1 – 25 of 35) sorted by relevance

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/u-boot/include/dt-bindings/clock/
A Dmicrochip-mpfs-clock.h25 #define CLK_SPI1 14 macro
A Dsun8i-a23-a33-ccu.h96 #define CLK_SPI1 71 macro
A Dsun5i-ccu.h74 #define CLK_SPI1 70 macro
A Dsun8i-a83t-ccu.h108 #define CLK_SPI1 71 macro
A Dactions,s700-cmu.h80 #define CLK_SPI1 55 macro
A Dsun50i-a64-ccu.h103 #define CLK_SPI1 81 macro
A Dsun8i-h3-ccu.h116 #define CLK_SPI1 83 macro
A Dactions,s900-cmu.h81 #define CLK_SPI1 63 macro
A Dsun50i-h616-ccu.h64 #define CLK_SPI1 78 macro
A Dsun9i-a80-ccu.h74 #define CLK_SPI1 48 macro
A Dsun50i-h6-ccu.h67 #define CLK_SPI1 81 macro
A Dsun6i-a31-ccu.h128 #define CLK_SPI1 94 macro
A Dsun8i-r40-ccu.h134 #define CLK_SPI1 114 macro
A Dsun4i-a10-ccu.h144 #define CLK_SPI1 113 macro
/u-boot/drivers/clk/sunxi/
A Dclk_a10s.c34 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_a10.c44 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_a23.c33 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_a64.c36 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_a80.c18 [CLK_SPI1] = GATE(0x434, BIT(31)),
A Dclk_a83t.c35 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_h6.c26 [CLK_SPI1] = GATE(0x944, BIT(31)),
A Dclk_a31.c41 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_h3.c41 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
A Dclk_h616.c28 [CLK_SPI1] = GATE(0x944, BIT(31)),
A Dclk_r40.c45 [CLK_SPI1] = GATE(0x0a4, BIT(31)),

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