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Searched refs:CLK_SRC_LEFTBUS_VAL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Dclock_init_exynos4.c51 writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); in system_clock_init()
A Dexynos4_setup.h155 #define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL) macro

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