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Searched refs:CLK_TOP_APLL12_DIV0 (Results 1 – 5 of 5) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8516-clk.h207 #define CLK_TOP_APLL12_DIV0 82 macro
A Dmt8518-clk.h216 #define CLK_TOP_APLL12_DIV0 67 macro
A Dmt8183-clk.h112 #define CLK_TOP_APLL12_DIV0 76 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8516.c723 GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
A Dclk-mt8518.c1443 GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),

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