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Searched refs:CLK_TOP_APLL12_DIV1 (Results 1 – 3 of 3) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8516-clk.h208 #define CLK_TOP_APLL12_DIV1 83 macro
A Dmt8183-clk.h113 #define CLK_TOP_APLL12_DIV1 77 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8516.c724 GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),

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